參數(shù)資料
型號(hào): IDT72T36125L5BBI
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 51/57頁(yè)
文件大小: 0K
描述: IC FIFO 524X18 5NS 240BGA
標(biāo)準(zhǔn)包裝: 1
系列: 72T
功能: 異步,同步
存儲(chǔ)容量: 9.4K(524 x 18)
數(shù)據(jù)速率: 83MHz
訪問(wèn)時(shí)間: 5ns
電源電壓: 2.375 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 240-BGA
供應(yīng)商設(shè)備封裝: 240-PBGA(19x19)
包裝: 托盤(pán)
其它名稱(chēng): 72T36125L5BBI
55
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the
EFandFF functionsinIDTStandardmodeandtheIR
and
ORfunctionsinFWFTmode. BecauseofvariationsinskewbetweenRCLK
and WCLK, it is possible for
EF/FF deassertion and IR/OR assertion to vary
by one cycle between FIFOs. In IDT Standard mode, such problems can be
avoided by creating composite flags, that is, ANDing
EF of every FIFO, and
separately ANDing
FF of every FIFO. In FWFT mode, composite flags can
be created by ORing
OR of every FIFO, and separately ORing IR of every
FIFO.
Figure 36 demonstrates a width expansion using two IDT72T3645/
72T3655/72T3665/72T3675/72T3685/72T3695/72T36105/72T36115/
72T36125 devices. D0 - D35 from each device form a 72-bit wide input bus and
Q0-Q35 from each device form a 72-bit wide output bus. Any word width can
be attained by adding additional IDT72T3645/72T3655/72T3665/72T3675/
72T3685/72T3695/72T36105/72T36115/72T36125 devices.
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 36. Block Diagram of 1,024 x 72, 2,048 x 72, 4,096 x 72, 8,192 x 72, 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 and 262,144 x 72
Width Expansion
WRITE CLOCK (WCLK)
m + n
mn
MASTER RESET (MRS)
READ CLOCK (RCLK)
DATA OUT
n
m + n
WRITE ENABLE (WEN)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE (PAF)
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
OUTPUT ENABLE (OE)
READ ENABLE (REN)
m
LOAD (LD)
IDT
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
72T36105
72T36115
72T36125
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PARTIAL RESET (PRS)
5907 drw41
FULL FLAG/INPUT READY (FF/IR) #2
HALF-FULL FLAG (HF)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
#1
FIFO
#2
GATE
(1)
GATE
(1)
D0 - Dm
DATA IN
Dm+1 - Dn
Q0 - Qm
Qm+1 - Qn
FIFO
#1
IDT
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
72T36105
72T36115
72T36125
READ CHIP SELECT (RCS)
SERIAL CLOCK (SCLK)
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