IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x" />
參數(shù)資料
型號: IDT72V3614L20PQF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 12/32頁
文件大?。?/td> 0K
描述: IC FIFO 64X36X2 20NS 132QFP
標準包裝: 36
系列: 72V
功能: 異步,同步
存儲容量: 4.6K(64 x 36 x2)
數(shù)據(jù)速率: 50MHz
訪問時間: 20ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 132-BQFP 緩沖式
供應商設備封裝: 132-PQFP(24.13x24.13)
包裝: 托盤
其它名稱: 72V3614L20PQF
IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIALTEMPERATURERANGE
2
TQFP (PNG120, order code: PF)
TOP VIEW
B22
B21
GND
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
GND
B9
B8
B7
VCC
B6
B5
B4
B3
GND
B2
B1
B0
EFB
AEB
AFB
A23
A22
A21
GND
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
GND
A9
A8
A7
VCC
A6
A5
A4
A3
GND
A2
A1
A0
EFA
AEA
4663 drw 03
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
91
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
AFA FFA
CSA ENA
CLKA
W/
R
A
V
CC
PGA
PEFA MBF
2
MBA
FS
1
FS
0
ODD/
EVEN
RST GND
BE
SW1
SW0
SIZ1 SIZ0
MBF
1
PEFB PGB
V
CC
W/
R
B
CLKB
ENB CSB
FFB
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
B
23
A
24
A
25
A
26
V
CC
A
27
A
28
A
29
GND
A
30
A
31
A
34
A
35
B
35
GND
B
34
B
33
B
32
B
30
B
31
GND
B
29
B
28
B
27
V
CC
B
26
B
25
B
24
A
32
A
33
DESCRIPTION:
TheIDT72V3614isdesignedtorunoffa3.3Vsupplyforexceptionallylow
powerconsumption. Thisdeviceismonolithic,high-speed,low-powerCMOS
bidirectionalclockedFIFOmemory.Itsupportsclockfrequenciesupto67MHz
andhasreadaccesstimesasfastas10ns.TheFIFOoperatesinIDTStandard
mode. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip
bufferdatainoppositedirections.EachFIFOhasflagstoindicateemptyand
fullconditionsandtwoprogrammableflags(Almost-FullandAlmost-Empty)to
indicatewhenaselectednumberofwordsisstoredinmemory. FIFOdataon
portBcanbeinputandoutputin36-bit,18-bit,and9-bitformatswithachoice
ofBig-orLittle-Endianconfigurations.Threemodesofbyte-orderswappingare
possiblewithanybussizeselection.Communicationbetweeneachportcan
bypasstheFIFOsviatwo36-bitmailboxregisters. Eachmailboxregisterhas
aflagtosignalwhennewmailhasbeenstored.Parityischeckedpassivelyon
eachportandmaybeignoredifnotdesired. Paritygenerationcanbeselected
PIN CONFIGURATION
for data read from each port. Two or more devices can be used in parallel to
createwiderdatapaths.
This device is a clocked FIFO, which means each port employs a
synchronousinterface.AlldatatransfersthroughaportaregatedtotheLOW-
to-HIGHtransitionofacontinuous(free-running)portclockbyenablesignals.
The clocks for each port are independent of one another and can be
asynchronousorcoincident.Theenablesforeachportarearrangedtoprovide
asimplebidirectionalinterfacebetweenmicroprocessorsand/orbusescon-
trolled by a synchronous interface.
The Full Flag (FFA, FFB) and Almost-Full flag (AFA, AFB) of a FIFO are
two-stagesynchronizedtotheportclockthatwritesdatatoitsarray. TheEmpty
Flag (EFA,EFB) and Almost-Empty (AEA,AEB) flag of a FIFO are two stage
synchronized to the port clock that reads data from its array.
The IDT72V3614 is characterized for operation from 0
°C to 70°C. This
deviceisfabricatedusinghighspeed,submicronCMOStechnology.
NOTE:
1. Pin 1 identifier in corner.
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