IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x" />
參數(shù)資料
型號: IDT72V3614L20PQF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 31/32頁
文件大?。?/td> 0K
描述: IC FIFO 64X36X2 20NS 132QFP
標準包裝: 36
系列: 72V
功能: 異步,同步
存儲容量: 4.6K(64 x 36 x2)
數(shù)據(jù)速率: 50MHz
訪問時間: 20ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 132-BQFP 緩沖式
供應(yīng)商設(shè)備封裝: 132-PQFP(24.13x24.13)
包裝: 托盤
其它名稱: 72V3614L20PQF
IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIALTEMPERATURERANGE
8
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and SIZ1, SIZ0 are HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
3. Only applies when a new port B bus size is implemented by the rising CLKB edge.
4. Only applies when reading data from a mail register.
IDT72V3614L15
Symbol
Parameter
Min.
Max.
Unit
tA
Access Time, CLKA
↑ to A0-A35 and CLKB↑ to B0-B35
2
10
ns
tWFF
Propagation Delay Time, CLKA
↑ to FFA and CLKB↑ to FFB
210
ns
tREF
Propagation Delay Time, CLKA
↑ to EFA and and CLKB↑ to EFB
210
ns
tPAE
Propagation Delay Time, CLKA
↑ to AEA and CLKB↑ to AEB
210
ns
tPAF
Propagation Delay Time, CLKA
↑ to AFA and CLKB↑ to AFB
210
ns
tPMF
Propagation Delay Time, CLKA
↑ to MBF1 LOW or MBF2 HIGH and CLKB↑ to
1
9
ns
MBF2 LOW or MBF1 HIGH
tPMR
Propagation Delay Time, CLKA
↑ to B0-B35(1)and CLKB↑ to A0-A35(2)
210
ns
tPPE(3)
Propagation delay time, CLKB
↑toPEFB
210
ns
tMDV
Propagation Delay Time, MBA to A0-A35 valid and SIZ1, SIZ0 to B0-B35 valid
1
10
ns
tPDPE
Propagation Delay Time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid
2
10
ns
tPOPE
Propagation Delay Time, ODD/EVEN to PEFA and PEFB
210
ns
tPOPB(4) Propagation Delay Time, ODD/EVEN to parity bits (A8, A17, A26, A35) and
2
10
ns
(B8, B17, B26, B35)
tPEPE
Propagation Delay Time, CSA, ENA,W/RA, MBA, or PGA to PEFA; CSB, ENB, W/RB,
1
10
ns
SIZ1, SIZ0, or PGB to PEFB
tPEPB(4) Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to parity bits (A8, A17, A26, A35);
2
10
ns
CSB, ENB, W/RB,SIZ1, SIZ0, or PGB to parity bits (B8, B17, B26, B35)
tRSF
Propagation Delay Time, RST to (MBF1, MBF2) HIGH
1
15
ns
tEN
Enable Time, CSA and W/RA LOW to A0-A35 active and CSB LOW and W/RB HIGH to
2
10
ns
B0-B35active
tDIS
Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and CSB HIGH or
1
8
ns
W/RB LOW to B0-B35 at high-impedance
Commercial: Vcc=3.3V± 0.30V; TA = 0
°C to +70°C; JEDEC JESD8-A compliant
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