IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x" />
參數(shù)資料
型號(hào)： IDT72V3614L20PQF
廠(chǎng)商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 32/32頁(yè)
文件大?。?/td> 0K
描述： IC FIFO 64X36X2 20NS 132QFP
標(biāo)準(zhǔn)包裝： 36
系列： 72V
功能： 異步，同步
存儲(chǔ)容量： 4.6K（64 x 36 x2）
數(shù)據(jù)速率： 50MHz
訪(fǎng)問(wèn)時(shí)間： 20ns
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 132-BQFP 緩沖式
供應(yīng)商設(shè)備封裝： 132-PQFP（24.13x24.13）
包裝： 托盤(pán)
其它名稱(chēng)： 72V3614L20PQF
IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH
BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2
COMMERCIALTEMPERATURERANGE
9
outputregister. WhentheEmptyFlagisLOW,theFIFOisemptyandattempted
FIFOreadsareignored.WhenreadingFIFO1withabyteorwordsizeonport
B, EFB is set LOW when the fourth byte or second word of the last long word
is read.
ThereadpointerofaFIFOisincrementedeachtimeanewwordisclocked
totheoutputregister. ThestatemachinethatcontrolsanEmptyFlagmonitors
a write-pointer and read-pointer comparator that indicates when the FIFO
memorystatusisempty,empty+1,orempty+2. AwordwrittentoaFIFOcan
be read to the FIFO output register in a minimum of three cycles of the Empty
Flagsynchronizingclock. Therefore,anEmptyFlagisLOWifawordinmemory
isthenextdatatobesenttotheFIFOoutputregisterandtwocyclesoftheport
clockthatreadsdatafromtheFIFOhavenotelapsedsincethetimetheword
was written. The Empty Flag of the FIFO is set HIGH by the second LOW-to-
HIGHtransitionofthesynchronizingclock,andthenewdatawordcanberead
to the FIFO output register in the following cycle.
ALOW-to-HIGHtransitiononanEmptyFlagsynchronizingclockbeginsthe
firstsynchronizationcycleofawriteiftheclocktransitionoccursattimetSKEW1
orgreaterafterthewrite. Otherwise,thesubsequentclockcyclecanbethefirst
synchronization cycle (see Figure 14 and 15).
FULL FLAG (FFA, FFB)
TheFullFlagofaFIFOissynchronizedtotheportclockthatwritesdatato
itsarray.WhentheFullFlagisHIGH,amemorylocationisfreeintheFIFOto
receivenewdata. NomemorylocationsarefreewhenthefullflagisLOWand
attemptedwritestotheFIFOareignored.
EachtimeawordiswrittentoaFIFO,thewritepointerisincremented.The
statemachinethatcontrolsaFullFlagmonitorsawrite-pointerandread-pointer
comparatorthatindicateswhentheFIFOmemorystatusisfull,full-1,orfull-2.
FromthetimeawordisreadfromaFIFO,thepreviousmemorylocationisready
tobewritteninaminimumofthreecyclesoftheFullFlagsynchronizingclock.
Therefore,aFullFlagisLOWiflessthantwocyclesoftheFullFlagsynchronizing
clockhaveelapsedsincethenextmemorywritelocationhasbeenread.The
secondLOW-to-HIGHtransitionontheFullFlagsynchronizationclockafterthe
readsetstheFullFlagHIGHandthedatacanbewritteninthefollowingclock
cycle.
ALOW-to-HIGHtransitiononaFullFlagsynchronizingclockbeginsthefirst
synchronizationcycleofareadiftheclocktransitionoccursattimetSKEW1or
greateraftertheread. Otherwise,thesubsequentclockcyclecanbethefirst
synchronization cycle (see Figure 16 and 17).
ALMOST-EMPTY FLAGS (AEA, AEB)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads
datafromitsarray. ThestatemachinethatcontrolsanAlmost-Emptyflagmonitors
a write-pointer and a read-pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-emptystateisdefinedbythevalueoftheAlmost-FullandAlmost-Empty
Offsetregister(X). Thisregisterisloadedwithoneoffourpresetvaluesduring
adevicereset(seeResetsection). AnAlmost-EmptyflagisLOWwhentheFIFO
containsXorlesslongwordsinmemoryandisHIGHwhentheFIFOcontains
(X+1) or more long words.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock
arerequiredafteraFIFOwritefortheAlmost-Emptyflagtoreflectthenewlevel
offill. Therefore,theAlmost-EmptyflagofaFIFOcontaining(X+1)ormorelong
wordsremainsLOWiftwocyclesofthesynchronizingclockhavenotelapsed
sincethewritethatfilledthememorytothe(X+1)level. AnAlmost-Emptyflag
issetHIGHbythesecondLOW-to-HIGHtransitionofthesynchronizingclock
aftertheFIFOwritethatfillsmemorytothe(X+1)level. ALOW-to-HIGHtransition
ofanAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchronization
SIGNAL DESCRIPTIONS
RESET
TheIDT72V3614isresetbytakingtheReset(RST)inputLOWforatleast
fourportAclock(CLKA)andfourportBclock(CLKB)LOW-to-HIGHtransitions.
The Reset input can switch asynchronously to the clocks. A device reset
initializestheinternalreadandwritepointersofeachFIFOandforcestheFull
Flags(FFA,FFB)LOW,theEmptyFlags(EFA,EFB)LOW,theAlmost-Empty
flags (AEA, AEB) LOW and the Almost-Full flags (AFA, AFB) HIGH. A reset
also forces the Mailbox Flags (MBF1, MBF2) HIGH. After a reset, FFA is set
HIGH after two LOW-to-HIGH transitions of CLKA and FFB is set HIGH after
twoLOW-to-HIGHtransitionsofCLKB. Thedevicemustberesetafterpower
up before data is written to its memory.
A LOW-to-HIGH transition on the RST input loads the Almost-Full and
Almost-Empty Offset register (X) with the values selected by the Flag Select
(FS0,FS1)inputs. Thevaluesthatcanbeloadedintotheregistersareshown
inTable1.FortherelevantResetandpresetvalueloadingtimingdiagram,see
Figure 5.
FIFO WRITE/READ OPERATION
ThestateofportAdataA0-A35outputsiscontrolledbytheportAChipSelect
(CSA) and the port A Write/Read select (W/RA). The A0-A35 outputs are in
the high-impedance state when either CSA or W/RA is HIGH. The A0-A35
outputsareactivewhenbothCSAandW/RAareLOW.DataisloadedintoFIFO1
fromtheA0-A35inputsonaLOW-to-HIGHtransitionofCLKAwhenCSAisLOW,
W/RAisHIGH,ENAisHIGH,MBAisLOW,andFFAisHIGH. Dataisreadfrom
FIFO2 to the A0-A35 outputs by a LOW-to-HIGH transition of CLKA when CSA
isLOW,W/RAisLOW,ENAisHIGH,MBAisLOW,andEFAisHIGH(seeTable
2). Port A read and write timing diagrams can be found in Figure 6 and 15.
The port B control signals are identical to those of port A. The state of the
portBdata(B0-B35)outputsiscontrolledbytheportBChipSelect(CSB)and
the port B Write/Read select (W/RB). The B0-B35 outputs are in the high-
impedancestatewheneitherCSBorW/RBisHIGH. TheB0-B35outputsare
activewhenbothCSBandW/RBareLOW.DataisloadedintoFIFO2fromthe
B0-B35inputson aLOW-to-HIGHtransitionofCLKBwhenCSBisLOW,W/
RBisHIGH,ENBisHIGH,EFBisHIGH,andeitherSIZ0orSIZ1isLOW. Data
isreadfromFIFO1totheB0-B35outputsbyaLOW-to-HIGHtransitionofCLKB
whenCSBisLOW,W/RBisLOW,ENBisHIGH, EFBisHIGH,andeitherSIZ0
orSIZ1isLOW(seeTable3).PortBreadandwritetimingdiagramstogether
withBus-Matching,byte-swappingandEndianselectcanbefoundinFigures
7 to 12.
ThesetupandholdtimeconstraintstotheportclocksfortheportChipSelects
(CSA,CSB)andWrite/Readselects(W/RA,W/RB)areonlyforenablingwrite
andreadoperationsandarenotrelatedtohigh-impedancecontrolofthedata
outputs. IfaportenableisLOWduringaclockcycle,theportChipSelectand
Write/Readselectcanchangestatesduringthesetupandholdtimewindowof
thecycle.
SYNCHRONIZED FIFO FLAGS
EachFIFOissynchronizedtoitsportclockthroughtwoflip-flopstages. This
isdonetoimproveflagreliabilitybyreducingtheprobabilityofmetastableevents
ontheoutputwhenCLKAandCLKBoperateasynchronouslytooneanother.
EFA, AEA, FFA, and AFA are synchronized to CLKA. EFB, AEB, FFB, and
AFBaresynchronizedtoCLKB. Tables4and5showtherelationshipofeach
port flag to the level of FIFO1 and FIFO2 fill.
EMPTY FLAGS (EFA, EFB)
TheEmptyFlagofaFIFOissynchronizedtotheportclockthatreadsdata
fromitsarray. WhentheEmptyFlagisHIGH,newdatacanbereadtotheFIFO
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