參數(shù)資料
型號： IDT77105
廠商： Integrated Device Technology, Inc.
英文描述： PHY (TC-PMD) for 25.6 Mbps ATM Networks
中文描述： 物理層（增距鏡TC - PMD）的25.6 Mbps的ATM網(wǎng)絡(luò)
文件頁數(shù)： 5/24頁
文件大小： 335K
代理商： IDT77105
5 of 24
September 11, 2000
IDT77105
22
23
24
RxSOC
RxEmpty/RxClav
RxRef
O
O
O
UTOPIA bus
UTOPIA bus
UTOPIA bus
Receive Start of Cell signal.
Receive Empty (active low; byte mode) or Receive Cell Available (active high; cell mode).
Receive Reference signal (active low). This pin is driven in response to a received X_8 command byte.
Assertion duration is programmable to 1,2,4 or 8 clocks, as set via register 0x03, bits 3,4.
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
V
CC
RxData0
RxData1
RxData2
RxData3
RxData4
RxData5
GND
RxData6
RxData7
RxParity
RxClk
RxEnb
TxFull/TxCLAV
TxSOC
TxEnb
TxClk
TxParity
TxData7
TxData6
TxData5
TxData4
TxData3
TxData2
TxData1
TxData0
TxRef
—
O
O
O
O
O
O
—
O
O
O
I
I
O
I
I
I
I
I
I
I
I
I
I
I
I
I
Power plane
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
Ground plane
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
Receive data bit 0.
Receive data bit 1.
Receive data bit 2.
Receive data bit 3.
Receive data bit 4.
Receive data bit 5.
Receive data bit 6.
Receive data bit 7.
Parity bit for RxData[7:0].
Receive data path synchronization clock.
Receive Enable signal (active low).
Transmit Full (active low; byte mode) or Transmit Cell Available (active high; cell mode).
Transmit Start of Cell signal.
Transmit Enable signal (active low).
Transmit data path synchronization clock.
Parity bit for TxData[7:0]. If unused, this pin must be tied high or low.
Transmit data bit 7.
Transmit data bit 6.
Transmit data bit 5.
Transmit data bit 4.
Transmit data bit 3.
Transmit data bit 2.
Transmit data bit 1.
Transmit data bit 0.
Transmit Reference signal input (active low). Assertion (falling edge) of this pin stimulates insertion of com-
mand byte X_8 into the transmit data stream.
Reset signal (active low).
Interrupt signal (active low). Always driven.
Address/Data bit 7. Not used for addressing.
Address/Data bit 6. Not used for addressing.
52
53
54
55
56
57
58
59
60
61
62
63
64
Reset
INT
AD7
AD6
VCC
AD5
AD4
AD3
AD2
AD1
AD0
GND
CS
I
O
I/O
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
—
I
control
control
Utility bus
Utility bus
Power plane
Utility bus
Utility bus
Utility bus
Utility bus
Utility bus
Utility bus
Ground plane
Utility bus
Address/Data bit 5. Not used for addressing.
Address/Data bit 4. Not used for addressing.
Address/Data bit 3. Not used for addressing.
Address/Data bit 2.
Address/Data bit 1.
Address/Data bit 0.
Utility Bus Chip select (active low).
Pin
Name
I/O
Interfaces to
Description
Table 1 Pin Description (Part 2 of 2)
相關(guān)PDF資料
PDF描述
IDT77155L155 PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
IDT77155 PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
IDT77155L155PX PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
IDT77301 UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77301L12PF UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT77105L25TFI 制造商:Integrated Device Technology Inc 功能描述:
IDT77155L155PX 制造商:INT_DEV_TECH 功能描述:
IDT77201L25PF 制造商:Integrated Device Technology Inc 功能描述:
IDT77211L155PQF 制造商:Integrated Device Technology Inc 功能描述:ATM/SONET SEGMENTATION AND REASSEMBLY CIRCUIT, 208 Pin, Plastic, QFP
IDT77V011L155DA 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*