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參數(shù)資料
| 型號(hào)： | IDT77105L25TFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | PHY (TC-PMD) for 25.6 Mbps ATM Networks |
| 中文描述： | ATM NETWORK INTERFACE, PQFP64 |
| 封裝： | 10 X 10 MM, STQFP-64 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大小： | 335K |
| 代理商： | IDT77105L25TFI |
8 of 24
September 11, 2000
IDT77105
Upon reset or line re-connect, the IDT77105 receiver is typically not
symbol-synchronized. Synchronization is established when it receives a
command byte, usually the start-of-cell command preceding the first
received cell.
The IDT77105 monitors line conditions and can provide an interrupt if
the line is deemed 'bad'. The interrupt status register contains a Good
Signal Bit (address 0x01, bit 6 set to 0 = Bad signal initially) which shows
the status of the line per the following algorithm:
To declare “Good Signal” (from "Bad" to "Good"):
There is an up-down counter that counts from 7 to 0 and is initially
set to 7. When the clock ticks for 1,024 cycles (32MHz clock, 1,024
cycles = 204.8 symbols) and no "bad symbol" has been received, the
counter decreases by one (i.e., from 7 to 6). However, if at least one
"bad symbol" is detected during these 1,024 clocks, the counter is
increased by one with a maximum of 7 (i.e., from 6 back to 7). The Good
Signal Bit is set to 1 when this counter reaches 0. The Good Signal Bit
could be set to 1 as quickly as 1,433 symbols (204.8 x 7) if no bad
symbols have been received.
To declare 'Bad Signal' (from "Good" to "Bad"):
The same up-down counter counts from 0 to 7 (being at 0 to provide
a "Good" status). When the clock ticks for 1,024 cycles (32MHz clock,
1,024 cycles = 204.8 symbols) and there is at least one "bad symbol",
the clock increases one (i.e., from 0 to 1). If it detects all "good symbols"
and no "bad symbols" in the next time period, the counter decreases one
(i.e., from 1 back to 0). The "Bad Signal" is declared when the counter
reaches 7. The Good Signal Bit could be set to 0 as quickly as 1,433
symbols (204.8 x 7) if at least one "bad symbol" is detected in each
204.8 symbols of seven consecutive groups of 204.8 symbols.
UTOPIA Interface
The 'UTOPIA' (Universal Test & Operations PHY Interface for ATM)
interface is used as the data path interface between the IDT77105 PHY
and other system elements such as the Segmentation and Reassembly
(SAR) device, or switching systems.
Overview
Cell data is transferred via separate Transmit and Receive synchro-
nizing clocks which are controlled by the SAR or other system compo-
nents. Transfer of data is synchronized at the cell level through the use
of a Start of Cell signal. This signal is asserted when the data transfer
path contains the first byte of a cell.
Since the PHY layer uses external clocks for data transfer synchroni-
zation, flow control signals are provided to allow both the external device
and the PHY to throttle the data transfer rate.
Receive data is transferred when the RxEnb signal is asserted by an
external device. The PHY also provides an RxEmpty signal to indicate
that no valid data is ready for transfer out of the PHY. This signal is
active if another read would cause a PHY buffer underflow. Along with
RxEmpty, RxClav (Receive Cell Available) indicates that a complete cell
has been received and is ready for transfer. Likewise, Transmit data is
also transferred using similar controls and handshake signals.
The Status and Control interface for the IDT77105 PHY is provided
to allow control of several functions such as Header Error Control (HEC)
processing, diagnostics, and error notification/management.
Figure 2
4
Octet
Interface
Control -
RECV
8
RxData
4
RxClk
RxEnb
RxEmpty
5
NRZI
Decoding
Rx +
Rx
4
4
PRNG
Scramble
Nibble
Next
Reset
RxSOC
RxRef
32.0MHz
Clock
Synthesizer
& PLL
5b/4b
Decoding
Command
Byte
Detection,
Removal,
& Decode
De-
Scrambler
3445 drw 04
OSC
2 Cells
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT77105 | PHY (TC-PMD) for 25.6 Mbps ATM Networks |
| IDT77155L155 | PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS |
| IDT77155 | PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS |
| IDT77155L155PX | PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS |
| IDT77301 | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT77155L155PX | 制造商:INT_DEV_TECH 功能描述: |
| IDT77201L25PF | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT77211L155PQF | 制造商:Integrated Device Technology Inc 功能描述:ATM/SONET SEGMENTATION AND REASSEMBLY CIRCUIT, 208 Pin, Plastic, QFP |
| IDT77V011L155DA | 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| IDT77V011L155DA8 | 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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