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參數(shù)資料
| 型號： | IDT77305 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | UTOPIAFIFO 4 PORT MULTIPLEXER FIFO |
| 中文描述： | 128 X 9 OTHER FIFO, 8.5 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 10/27頁 |
| 文件大小： | 248K |
| 代理商： | IDT77305 |
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IDT77305
UtopiaFIFO 4 to 1 (128 x 9 x 4) Multiplexer-FIFO Commercial and Industrial Temperature Ranges
Preliminary
10
TABLE 1: Truth table for cell size programming
Note values are loaded on the rising edge of
RST
mux select lines provide user control of FIFO selection.
+
SINGLE DEVICE OPERATION
The two programmable interface signaling modes of operation are
Utopia Receive (UtopiaRx) and Utopia transmt (UtopiaTx). Both modes
can concentrate four nine-bit channels (up to 720 Mbs) to one 18-bit output
channel (up to 1.44 Gbs). In a building block implementation, multiple
streams over 10 Gbs (with 32, 64, or 128 bit buses) can be obtained. Mode
one, UtopiaRx, follows UtopiaRx protocols; and Mode two, UtopiaTx,
follows UtopiaTx protocols. The Receive/Transmt Select (RTS) pin sets
the UtopiaFIFO into the desired mode. The difference between these
modes relates to the Utopia specification for signal handshaking. In
UtopiaRx mode, the device receiving data controls the data flow through
ENR (or
ENS
on the output side). In UtopiaTx mode, the device sending
data controls the data flow through ENR (or
ENS
on the output side). This
is described in the Utopia ATM-PHY Level2 version 1 Document.
In either mode, data is transferred in "cells". ATMcell size is 53 bytes.
However, for applications other than ATMthe cell size can be programmed
through the cell size register. Programmng this register allows cell sizes
from8 bytes to 128 bytes. With
RST
and
OE
both HIGH, CR(0-3), CSS,
ECT and CRC are cell size inputs. The default cell size of 53 bytes is
selected when both
RST
and
OE
are LOW. In either case the values
are latched on the rising edge of
RST
. To load a specific cell size value
from8 bytes to 128 bytes use CR(0-3), CSS, ECT and CRC as inputs with
RST
and
OE
both HIGH. The bit order is CR0, CR1, CR2, CR3, CSS,
ECT, CRC, with CR0 being LSB and CRC being MSB. Set all input pins
LOW to programa cell size of 128 bytes. See Table 1 for cell size
programmng truth table.
Control signals for the input data (receive) side consists of
CLAVR,
ENR
and SOCR (see Table 2a). Prior to cell transfer, the
controlling agent (data source for transmt mode, data destination for
receive mode) is notified a cell transfer can take place through the assertion
of the CLAVR signal. Each data transfer of a cell is completed by assertion
of
ENR
. The
ENR
signal is supplied by the controlling agent. During the
first data byte transfer, the data source asserts SOCR to mark the beginning
of the cell. Data transfer continues until the cell is completed. When the cell
size is reached, further writes are blocked until new CLAVR and SOCR
signals are received.
RXMODE
In UtopiaRx mode (see Figure 2a),
ENR
is an output to the sending
device and assertion of
ENR
results in data writes to the UtopiaFIFO in a
pipelined fashion. Once enabled, data is written on the following rising clock
edge. CLAVR controls data fromthe sender side. While this signal remains
HIGH, data is valid. If CLAVR goes LOW, data continues to be valid after
cell transfer is started. After cell transfer begins, if
ENR
is deasserted, data
writes halt until subsequent assertions (see Figures 3).
The I/O status of the output pins are listed in Table 3 for both UtopiaRx
and UtopiaTx modes in either Master or Slave configuration. As a stand-
alone device, the UtopiaFIFO has The I/O status of the output pins are listed
in Table 3 for both UtopiaRx and UtopiaTx modes in either Master or
Slave configuration. As a stand-alone device, the UtopiaFIFO has
the same description as shown for a device in a master setting
—
the
MSE signal is set HIGH (slave operation is described later in building
block mode section).
In UtopiaTx mode, the CLAVS is an input to the UtopiaFIFO
signaling a complete cell can be transferred. As the controlling
agent, the UtopiaFIFO asserts an output signal,
ENS
to transfer data
on the same rising clock edge (see Figure 6).
ADDITIONAL CONTROL SIGNALS—RX AND TX MODES
Three additional control signals provide added device functionality.
The global reset (
RST
) pin clears all register values. The byte swapping
(SWP) pin provides the ability to swap byte positions on the output. SWP
is a dynamc signal
—
once this signal is changed, output high and low bytes
are swapped on the next clock cycle. If SWP is high the first byte of data
is put in the upper byte of output bus, and if low the first byte is placed in
the lower byte. SWP high will make the output bus Utopia compliant. The
function is disabled when output bus size is set to 9-bits. The Byte Delete/
Insert (BDI) pin enables byte delete/insert to comply with ATMbus
matching. The input bus is Utopia compliant 9-bit bus with the output an 18-
bit bus. Data is transferred to each FIFO in 53 byte cells. The Utopia spec
defines 53 bytes per cell for 8-bit transfer and 54 bytes per cell for 16 bit
transfer. Compatibility with 53 byte ATMcell formatting during bus matching
is maintained. With the BDI selected, depending on the byte size and
interface signaling mode, the UtopiaFIFO will automatically insert and/or
delete dummy or header bytes according to Table 4; thus maintaining data
integrity and Utopia specification compatibility. With BDI asserted HIGH, cell
size is limted to 126 bytes. When output bus size is set to 9-bits, BDI must
be deasserted LOW.
The round robin sequencer sequentially selects one of four FIFOs
to output data. The sequencer is enabled by asserting the Round
Robin Enable (RRE) HIGH. The sequencer will poll each FIFO in turn
to determne which has data to send and selects the appropriate FIFO.
FUNCTION
1
0
CR(0-3), CSS, ECT, CRC are cell size inputs
0
0
sets default cell size of 53 bytes
1
1
CR(0-3), CSS ECT, CRC are tristated
0
1
CR(0-3), CSS, ECT, CRC are outputs
CR(0-3) = "0" then no cell in FIFO
= "1" then cell in FIFO
CSS = no function: don't care
ECT asserts one cycle before the end of a cell
transfer
CRC = "0" then no FIFO(s) has a cell
CRC = "1" then at least one FIFO has cell
3206 tbl 14
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