參數(shù)資料
型號: IDT77305
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: UTOPIAFIFO 4 PORT MULTIPLEXER FIFO
中文描述: 128 X 9 OTHER FIFO, 8.5 ns, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
文件頁數(shù): 2/27頁
文件大?。?/td> 248K
代理商: IDT77305
IDT77305
UtopiaFIFO 4 to 1 (128 x 9 x 4) Multiplexer-FIFO Commercial and Industrial Temperature Ranges
Preliminary
2
* +
The IDT77305 UtopiaFIFO is a high-speed, low power, four to one,
muxed FIFO with multiple programmable modes of operation. The
IDT77305 can be used as a stand alone device or as a building block
element. Within the UtopiaFIFO, the input FIFOs act as intermediate
queues for the input streams to allow synchronization with a common output
stream(see Functional Block Diagram. Each of the four input synchro-
nous (clocked) FIFOs are 64 words (128 bytes) in depth. Separate input
and output clocks are supported to 80 MHz. As a stand alone element four
independent 9-bit input streams are concentrated onto one selectable 9
or 18-bit output bus. The Bus Size Select pin (BSS) determnes the
desired output bus width. In a building block configuration, multiple
devices can be used to multiplex larger numbers of input streams
onto output buses greater than 18 bits. The principle application is
in ATMnetworking based systems, but can be used in any data or
telecommunications application requiring the merging of indepen-
dent data streams into a single output.
FIFO selection for data output can be made internally via a round robin
which sequentially selects one of the four FIFOs. Alternatively, external
100 PIN
TQFP
PN-100
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3206 drw 02
Q
12
Q
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Q
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Q
9
Vcc
Q
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Q
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Q
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Q
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GND
Q
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Q
3
Q
2
Q
1
Q
0
Q
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GND
Q
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Q
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Q
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Q
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Vcc
SOCS
CLAVS
SOCR d
Data d 8
GND
Data d 7
Data d 6
Data d 5
Data d 4
Data d 3
Data d 2
Data d 1
Data d 0
c
CLAVR c
SOCR c
Data c 8
Data c 7
Data c 6
Data c 5
Data c 4
Vcc
Data c 3
Data c 2
Data c 1
Data c 0
b
C
d
W
B
V
R
B
C
0
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1
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2
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3
C
E
C
M
R
L
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2
M
1
R
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G
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a
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V
C
,
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