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參數(shù)資料
| 型號： | IDT77305 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | UTOPIAFIFO 4 PORT MULTIPLEXER FIFO |
| 中文描述： | 128 X 9 OTHER FIFO, 8.5 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 15/27頁 |
| 文件大小： | 248K |
| 代理商： | IDT77305 |
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IDT77305
UtopiaFIFO
4 to 1 (128 x 9 x 4) Multiplexer-FIFO Commercial and Industrial Temperature Ranges
()!21/AB<(
All first Rank UtopiaFIFOs are set as Masters with the second Rank
having one Master and one Slave. The master/slave control signal-
ing for the Rx mode is shown in Figure 10c. After the Mux select
signals are set, they are loaded into the Slave fromthe Master on the
LDMrising clock edge. Once the mux signals are loaded either
externally or internally via Round Robin Sequencer, the CLAVS from
either Rank 1 or Rank 2 devices goes HIGH once a cell is available.
The receiving systemmust issue an active
ENS
signal once it can
accept a cell. When the CLAVS fromRank 2 and the receiving
ENS
signal are both asserted, data will be put on the output bus (fromboth
the Master and Slave devices) on the clock cycle following assertion
of
ENS
. In this setup,
ENS
fromthe receiving systemMUST be
asserted when it can accept data regardless of the CLAVS signals (the
target must not monitor CLAVS before asserting
ENS
). As shown in Figure
10c, if
ENS
is low prior to CLAVS assertion, then once CLAVS is asserted,
data is placed on the 36-bit bus on the same cycle. If CLAVS is asserted
before
ENS
, then once
ENS
is active, data is placed on the output bus on
the next cycle. With the first output word, SOCS is asserted for one cycle.
Data is synchronized between the Master and Slave internally. The Master
will assert LDMand Mux1 and Mux2 to the Slave two cycles prior to data
transfer to allow the Slave time to transfer data through internal registers;
it places data on the output bus two cycles later. The receiving systemcan
throttle data via the
ENS
signal.
BUILDING BLOCK MODE: 16 CHANNELS TO ONE 36-BIT
OUTPUT CHANNEL FOR TX SIGNALS
In transmt Utopia mode, the data transmtter controls data flow. For the
case of 16 channels to one 36-bit output channel, the second rank
of UtopiaFIFOs controls data flow to the downstreamsystemvia the
ENS
signals. The data flow fromrank 1 to rank 2 is controlled by rank
1. Data flow into rank 1 is controlled by the upstreamsystemas
described earlier for a single device mode. This signal control is
shown in Figure 10d. Initially, the Mux select lines for the Master
(either via round robin or through external selection) are selected
and then loaded into the Slave on the rising edge of LDM. Once both
ENS
fromthe Master and CLAVS fromthe receiver are asserted,
valid data is placed on the bus in 2 cycles. Data fromthe Slave is
placed on the bus two cycles after the LDMsignal is received and
when CLAVS is asserted. For the first data word, SOCS is asserted.
Until an entire cell is transferred, CLAVS can be HIGH or LOW. The
transmtting device starts to monitor the CLAVS signal four cycles prior to
a completed cell transfer. If the receiving device (either downstreamsystem
or rank 1 or rank 2 devices) cannot accept another cell transfer, it must de-
assert the CLAVS signal no later than this cycle. The Utopia FIFO devices
will determne if a second cell can be sent on the second cycle prior to last
word transfer.
(1)>B
After the start of cell signal (SOCR) is received, future SOCR assertions
prior to the end of current cell transfers are ignored. A counter keeps track
of byte transfer. If a "short cell" occurs (where a SOCR signal is received
prior to the end of cell transfer), the SOCR is ignored and the data from
the next incomng cell is loaded into the existing "short cell" until it is filled
to normal cell size. Any additional bytes fromthe incomng cell are ignored.
The short cell and next subsequent cell contents are bad data. Recovery
occurs on the third incomng cell. If a "long cell" occurs (where the number
of bytes exceeds the defined cell size and no new SOCR signal received
indicating a new cell), the extra bytes are ignored by the UtopiaFIFO. The
FIFO receiving the long cell will wait for a new SOCR (and assertion of
ENR
and CLAVR) before continuing data transfer.
Mode
Tx/Rx Mode
Byte Size
Ins/Del Selected
Result
1
Dont Care
Even
0
No added or deleted bytes
2
Dont Care
Odd
0
Byte insert to last high byte position
3
Tx
Even
1
Delete byte 5, insert byte to last high byte position
4
Rx
Even
1
Insert byte 6, insert byte to last high byte position
5
Tx
Odd
1
Delete byte 5
6
Rx
Odd
1
Insert byte 6
3206 tbl 18
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