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參數(shù)資料
| 型號(hào)： | IDT77305 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | UTOPIAFIFO 4 PORT MULTIPLEXER FIFO |
| 中文描述： | 128 X 9 OTHER FIFO, 8.5 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 4/27頁 |
| 文件大小： | 248K |
| 代理商： | IDT77305 |
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IDT77305
UtopiaFIFO 4 to 1 (128 x 9 x 4) Multiplexer-FIFO Commercial and Industrial Temperature Ranges
Preliminary
4
+#,-'
Name
I/O
Description
LDM
I/O
Load Mux. RRE = "1" and MSE = "1": LDM is an output telling Slave to latch the Mux select address on the next
clock cycle, RRE = "0" and MSE = "1": LDMis an input that latches the Mux address for the next cell transfer
MSE
I
Master/Slave Enable. MSE = "1" master mode, MSE = "0" slave mode.
MUX1
I/O
MUX1 address. With RRE = "1": MUX1 outputs FIFO address LSB: wth RRE = "0": MUX1 is input address LSB of
selected FIFO.
MUX2
I/O
MUX2 address. With RRE = "1": MUX2 outputs FIFO address MSB: wth RRE = "0": MUX2 is input addre MSB of
selected FIFO.
I
Output Enable. In combination with RST, it sets CR0-3 as either output cell available signals, input cell size values or
tri-state outputs (see Table 1).
Qn
O
Data bus output.
RCLK
I
Data read clock.
RRE
I
Round Robin Enable. RRE = "1" round robin sequencer enabled. RRE = "0" sets mux select lines and LDM as
inputs to provide user control over selected FIFO.
I
Reset. Clears all FIFO memory locations, read/write pointers, RR sequencer
RTS
I
Receive/Transmt mode Selection RTS = "0" Utopia Rx mode, RTS = "1" UtopiaTx mode.
SOCR a
I
Start Of Cell (FIFO-a)
—
Receive side. Active on first byte when CLAVR and
SOCR is ignored until full cell has been received.
are asserted. After first byte read,
SOCR b
I
Start Of Cell (FIFO-b)
—
Receive side. Active on first byte when CLAVR and
SOCR is ignored until full cell has been received.
are asserted. After first byte read,
SOCR c
I
Start Of Cell (FIFO-c)
—
Receive side. Active on first byte when CLAVR and
SOCR is ignored until full cell has been received.
are asserted. After first byte read,
SOCR d
I
Start Of Cell (FIFO-d)
—
Receive side. Active on first byte when CLAVR and
SOCR is ignored until full cell has been received.
are asserted. After first byte read,
SOCS
O
Start of Cell (sender side). Assertion: first word is currently on output bus.
SWP
I
Swap Enable. Swaps high byte and lowbyte of current word. SWP = "0": First word is placed in lower byte (Q0-Q7)
of 16-bit output (little endian), SWP = "1": first word is placed in upper byte (Q9-Q16) of 16-bit output (big endian
Utopia compliant cell format).
V
CC
____
Logic and supply V
CC
.
WCLK
I
Data write clock.
I
Data bus output enable.
3206 tbl 02
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