參數(shù)資料
型號(hào)： IDT77V1254L25
廠商： Integrated Device Technology, Inc.
英文描述： Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks
中文描述： 四端口PHY（實(shí)體層）為25.6和51.2 ATM網(wǎng)絡(luò)
文件頁數(shù)： 1/47頁
文件大?。?/td> 840K
代理商： IDT77V1254L25
1 of 47
September 21, 2001
2001 Integrated Device Technology, Inc.
DSC 6003
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
Quad Port PHY (Physical Layer)
for 25.6 and 51.2
ATM Networks
Features List
Performs the PHY-Transmission Convergence (TC) and
Physical Media Dependent (PMD) Sublayer functions for
four 25.6 Mbps ATM channels
Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5
specifications for 25.6 Mbps physical interface
Also operates at 51.2 Mbps data rate
UTOPIA Level 1, UTOPIA Level 2, or DPI-4 Interface
3-Cell Transmit & Receive FIFOs
LED Interface for status signalling
Supports UTP Category 3 and 5 physical media
Interfaces to standard magnetics
Low-Power CMOS
3.3V supply with 5V tolerant inputs
144-pin PQFP Package (28 x 28 mm)
Commercial and Industrial Temperature Ranges
Description
The IDT77V1254L25 is a member of IDT's family of products
supporting Asynchronous Transfer Mode (ATM) data communications
and networking. The IDT77V1254L25 implements the physical layer for
25.6 Mbps ATM, connecting four serial copper links (UTP Category 3
and 5) to one ATM layer device such as a SAR or a switch ASIC. The
IDT77V1254L25 also operates at 51.2 Mbps, and is well suited to back-
plane driving applications.
The 77V1254L25-to-ATM layer interface is selectable as one of three
options: 16-bit UTOPIA Level 2, 8-bit UTOPIA Level 1 Multi-PHY, or
quadruple 4-bit DPI (Data Path Interface).
The IDT77V1254L25 is fabricated using IDT's state-of-the-art CMOS
technology, providing the highest levels of integration, performance and
reliability, with the low-power consumption characteristics of CMOS.
Block Diagram
R X C LK
C lock R ecovery
5B /4B
E ncoding/
D ecoding
P /S and S /P
N R ZI
S cram bler/
D escram bler
TX /R X A TM
C ellFIFO
TX 0
R X 0
C lock R ecovery
5B /4B
E ncoding/
D ecoding
P /S and S /P
N R ZI
S cram bler/
D escram bler
TX /R X A TM
C ellFIFO
Tx 1
R x 1
C lock R ecovery
5B /4B
E ncoding/
D ecoding
P /S and S /P
N R ZI
S cram bler/
D escram bler
TX /R X A TM
C ellFIFO
TX 2
R X 2
C lock R ecovery
5B /4B
E ncoding/
D ecoding
P /S and S /P
N R ZI
S cram bler/
D escram bler
TX /R X A TM
C ellFIFO
TX 3
R X 3
P H Y -A TM
Interface
(U TO P IA orD P I)
M icroprocessor
Interface
TX D A TA [15:0]
TX P A R ITY
TX C LK
TXEN
R X D A TA [15:0]
R X P A R ITY
RXEN
4
4
R X LE D [3:0]
TX LE D [3:0]
RXREF
TXREF
TX A D D R [4:0]
R X A D D R [4:0]
+
-
+
-
+
-
+
-
+
-
+
-
TX S O C
TX C LA V
M O D E [1:0]
R X S O C
R X C LA V
3505 drw 01
+
-
+
-
INT
RST
RD
WR
CS
A LE
A D [7:0]
O S C
D river
D river
D river
D river
.
IDT77V1254L25
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