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參數(shù)資料
| 型號： | IDT77V1254L25 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks |
| 中文描述： | 四端口PHY（實體層）為25.6和51.2 ATM網(wǎng)絡(luò) |
| 文件頁數(shù)： | 7/47頁 |
| 文件大?。?/td> | 840K |
| 代理商： | IDT77V1254L25 |
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7 of 47
September 21, 2001
IDT77V1254L25
8-BIT UTOPIA Level 1 Signals (MODE[1:0] = 01)
Signal Name
Pin Number
I/O
Signal Description
RXCLAV[3:0]
64, 65, 66, 54
Out
Utopia 1 Receive Cell Available. Indicates the cell available status of the respective port. It is asserted when
a full cell is available for retrieval from the receive FIFO.
RXCLK
46
In
Utopia 1 Receive Clock. This is a free running clock input.
RXDATA[7:0]
69, 70, 71, 72, 73, 74, 75, 76 Out
Utopia 1 Receive Data. When one of the four ports is selected, the 77V1254L25 transfers received cells to an
ATM device across this bus. Bit 5 in the Diagnostic Control Registers determines whether RXDATA tri-states
when RXEN[3:0] are high. Also see RXPARITY.
RXEN[3:0]
51, 49, 48, 47
In
Utopia 1 Receive Enable. Driven by an ATM device to indicate its ability to receive data across the RXDATA
bus. One for each port
RXPARITY
58
Out
Utopia 1 Receive Data Parity. Odd parity over RXDATA[7:0].
RXSOC
55
Out
Utopia 1 Receive Start of Cell. Asserted coincident with the first word of data for each cell on RXDATA. Tri-
statable as determined by bit 5 in the Diagnostic Control Registers.
TXCLAV[3:0]
39, 40, 41, 42
Out
Utopia 1 Transmit cell Available. Indicates the availability of room in the transmit FIFO of the respective port
for a full cell.
TXCLK
43
In
Utopia 1 Transmit Clock. This is a free running clock input.
TXDATA[7:0]
24, 23, 22, 21, 20, 19, 18, 17 In
Utopia 1 Transmit Data. An ATM device transfers cells across the bus to the 77V1254L25 for transmission.
Also see TXPARITY.
TXEN[3:0]
27, 26, 25, 34
In
Utopia 1 Transmit Enable. Driven by an ATM device to indicate it is transmitting data across the TXDATA
bus. One for each port.
TXPARITY
33
In
Utopia 1 Transmit Data Parity. Odd parity across TXDATA[7:0]. Parity is checked and errors are indicated in
the Interrupt Status Registers, as enabled in the Master Control Registers. No other action is taken in the
event of an error. Tie high or low if unused.
TXSOC
35
In
Utopia 1 Transmit Start of Cell. Asserted coincident with the first word of data for each cell on TXDATA.
DPI Mode Signals (MODE[1:0] = 10)
Signal Name
Pin Number
I/O
Signal Description
DPICLK
43
In
DPI Source Clock for Transmit. This is the free-running clock used as the source to generate Pn_TCLK.
Pn_RCLK
52, 51, 49, 48
In
DPI Port ’n’ Receive Clock. Pn_RCLK is cycled to indicate that the interfacing device is ready to receive a
nibble of data on Pn_RD[3:0] of port ’n’.
Pn_RD[3:0]
59, 60, 61, 62, 63, 64, 65,
66, 69, 70, 71, 72, 73, 74,
75, 76
Out
DPI Port ’n’ Receive Data. Cells received on port ’n’ are passed to the interfacing device across this bus.
Each port has its own dedicated bus.
Pn_RFRM
53, 58, 54, 55
Out
DPI Port ’n’ Receive Frame. Pn_RFRM is asserted for one cycle immediately preceding the transfer of each
cell on Pn_RD[3:0].
Pn_TCLK
37, 39, 40, 41
Out
DPI Port ’n’ Transmit Clock. Pn_TCLK is derived from DPICLK and is cycled when the respective port is
ready to accept another 4 bits of data on Pn_TD[3:0].
Pn_TD[3:0]
32, 31, 30, 29, 28, 27, 26,
25, 24, 23, 22, 21, 20, 19,
18, 17
In
DPI Port ’n’ Transmit Data. Cells are passed across this bus to the PHY for transmission on port ’n’. Each
port has its own dedicated bus.
Pn_TFRM
36, 33, 34, 35
In
DPI Port ’n’ Transmit Frame. Start of cell signal which is asserted for one cycle immediately preceding the
first 4 bits of each cell on Pn_TD[3:0].
Table 1 Signal Descriptions (Part 3 of 3)
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