參數(shù)資料
型號： IDT77V1254L25
廠商： Integrated Device Technology, Inc.
英文描述： Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks
中文描述： 四端口PHY（實體層）為25.6和51.2 ATM網(wǎng)絡(luò)
文件頁數(shù)： 36/47頁
文件大?。?/td> 840K
代理商： IDT77V1254L25
36 of 47
September 21, 2001
IDT77V1254L25
Low Byte Counter Registers [7:0]
High Byte Counter Registers [15:8]
Counter Select Registers
Note:
For proper operation, only one bit may be set in a Counter Select Register at any time.
Interrupt Mask Registers
Note:
When set to "1", these bits mask the corresponding interrupts going to the interrupt pin (INT). When set to "0", the interrupts are
unmasked. These interrupts correspond to the interrupt status bits in the Interrupt Status Registers.
Addresses: 0x04, 0x14, 0x24, 0x34
Bit
Type
Initial State
Function
[7:0]
R
0x00
Provides low byte of counter value selected via registers 0x06, 0x16, 0x26, and 0x36
Addresses: 0x05, 0x15, 0x25, 0x35
Bit
Type
Initial State
Function
[7:0]
R
0x00
Provides high-byte of counter value selected via registers 0x06, 0x16, 0x26, and 0x36
Addresses: 0x06, 0x16, 0x26, 0x36
Bit
Type
Initial State
Function
7
—
—
Reserved.
6
—
—
Reserved.
5
—
—
Reserved.
4
—
—
Reserved.
3
W
0
Symbol Error Counter.
2
W
0
TXCell Counter.
1
W
0
RXCell Counter. Cells with HEC errors are never counted.
0
W
0
Receive HEC Error Counter.
Addresses: 0x07, 0x17, 0x27, 0x37
Bit
Type
Initial State
Function
7
0
Reserved.
6
0
Reserved.
5
R/W
0 = interrupt enabled
HEC Error Cell.
4
R/W
0 = interrupt enabled
Short Cell Error.
3
R/W
0 = interrupt enabled
Transmit Parity Error.
2
R/W
0 = interrupt enabled
Receive Signal Condition Change.
1
R/W
0 = interrupt enabled
Receive Cell Symbol Error.
0
R/W
0 = interrupt enabled
Receive FIFO Overflow.
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