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參數資料
| 型號： | IDT77V1254L25L25PG |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks |
| 中文描述： | 四端口PHY（實體層）為25.6和51.2 ATM網絡 |
| 文件頁數： | 24/47頁 |
| 文件大?。?/td> | 840K |
| 代理商： | IDT77V1254L25L25PG |
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24 of 47
September 21, 2001
IDT77V1254L25
In the transmit direction (ATM to PHY), the ATM layer device asserts start-of-cell signal (Pn_TFRM) for one clock cycle, one clock prior to driving
the first nibble of the cell on Pn_TD[3:0]. Once the ATM side has begun sending a cell, it is prepared to send the entire cell without interruption. The
77V1254L25 drives the transmit DPI clocks (Pn_TCLK) back to the ATM device, and can modulate (gap) it to control the flow of data. Specifically, if it
cannot accept another nibble, the 77V1254L25 disables Pn_TCLK and does not generate another rising edge until it has room for the nibble.
Pn_TCLK are derived from the DPICLK free running clock source.
The DPI protocol is exactly symmetrical in the receive direction, with the 77V1254L25 driving the data and start-of-cell signals while receiving
Pn_RCLK as an input.
The DPI data interface is four bits, so the 53 bytes of an ATM cell are transferred in 106 cycles. Figure 22 shows the sequence of that data transfer.
igures 23 through 30 show how the handshake operates.
Figure 22 DPI Data Format and Sequence
Figure 23 DPI Receive Handshake - One Cell Received
Figure 24 DPI Receive Handshake - Back-to-Back Cells
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;00 0 B "
;00 0 B %
;00 0 B "
;00 0 B %
;00 0 B "
;00 0 "B %
;00 0 "B "
;00 0 B %
;00 0 B "
' 0 B %
' 0 B "
' 0 "$B %
' 0 "$B "
' 0 "%B %
' 0 "%B "
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