參數(shù)資料
型號(hào)： IDT77V1254L25L25PG
廠商： Integrated Device Technology, Inc.
英文描述： Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks
中文描述： 四端口PHY（實(shí)體層）為25.6和51.2 ATM網(wǎng)絡(luò)
文件頁數(shù)： 37/47頁
文件大?。?/td> 840K
代理商： IDT77V1254L25L25PG
37 of 47
September 21, 2001
IDT77V1254L25
Enhanced Control 1 Registers
RXREF and TXREF Control Register
Absolute Maximum Ratings
Note:
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Addresses: 0x08, 0x18, 0x28, 0x38
Bit
Type
Initial State
Function
7
W
0 = not reset
Individual Port Software Reset 1= Reset.
This bit is self-cleaning; It isn’t necessary to write “0” to exit reset.
6
R/W
0 = OSC
Transmit Line Clock (or Loop Timing Mode).
When set to 0, the OSC input is used as the transmit line clock.
When set to 1, the recovered receive clock is used as the transmit line clock.
5
R/W
0
Reserved
4-0
R/W
Port 0 (Reg 0x08) 00000
Port 1 (Reg 0x18) 00001
Port 2 (Reg 0x28) 00010
Port 3 (Reg 0x38) 00011
Utopia 2 Port Address
When operating in Utopia 2 Mode, these register bits determine the Utopia 2 port address
Addresses: 0x40
Bit
Type
Initial State
Function
7-6
R/W
0 = RXREF0 (Port 0)
RXREF Source Select
Selects which of the four ports (0-3) is the source of RXREF.
5
W
0 = not reset
Master Software Reset
1 = Reset. This bit is self-cleaning; it isn’t necessary to write “0” to exit reset.
4
0
Reserved
3-0
R/W
0000 = not looped
RXREF to TXREF Loop Select
When set to 0, TXREF is used to generate X_8 timing marker commands.
When set to 1, TXREF input is ignored, and received X_8 timing commands.
are looped back and added to the transmit stream of that same port. See Figure 7.
bit 3: port 3
bit 2: port 2
bit 1: port 1
bit 0: port 0
Symbol
Rating
Value
Unit
VTERM
Terminal Voltage with Respect to GND
-0.5 to +5.5
V
TBIAS
Temperature Under Bias
-55 to +125
°
C
TSTG
Storage Temperature
-55 to +120
°
C
IOUT
DC Output Current
50
mA
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