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參數(shù)資料
| 型號： | IDT77V1254L25L25PG |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks |
| 中文描述： | 四端口PHY（實體層）為25.6和51.2 ATM網(wǎng)絡(luò) |
| 文件頁數(shù)： | 5/47頁 |
| 文件大小： | 840K |
| 代理商： | IDT77V1254L25L25PG |
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September 21, 2001
IDT77V1254L25
Signal Descriptions
Line Side Signals
Signal Name
Pin Number
I/O
Signal Description
RX0+,-
139, 138
In
Port 0 positive and negative receive differential input pair.
RX1+,-
133, 132
In
Port 1 positive and negative receive differential input pair.
RX2+,-
121, 120
In
Port 2 positive and negative receive differential input pair.
RX3+,-
115, 114
In
Port 3 positive and negative receive differential input pair.
TX0+,-
4, 3
Out
Port 0 positive and negative transmit differential output pair.
TX1+,-
144, 143
Out
Port 1 positive and negative transmit differential output pair.
TX2+,-
110, 109
Out
Port 2 positive and negative transmit differential output pair.
TX3+,-
106, 105
Out
Port 3 positive and negative transmit differential output pair.
Utility Bus Signals
Signal Name
Pin Number
I/O
Signal Description
AD[7:0]
101, 100, 99, 98, 96, 95, 94,
93
In/Out
Utility bus address/data bus. The address input is sampled on the falling edge of ALE. Data is output on this
bus when a read is performed. Input data is sampled at the completion of a write operation.
ALE
91
In
Utility bus address latch enable. Asynchronous input. An address on the AD bus is sampled on the falling
edge of ALE. ALE must be low when the AD bus is being used for data.
CS
90
Utility bus asynchronous chip select. CS must be asserted to read or write an internal register. It may remain
asserted at all times if desired
RD
89
In
Utility bus read enable. Active low asynchronous input. After latching an address, a read is performed by
deasserting WR and asserting RD and CS.
WR
88
In
Utility bus write enable. Active low asynchronous input. After latching an address, a write is performed by
deasserting RD, placing data on the AD bus, and asserting WR and CS. Data is sampled when WR or CS is
deasserted.
Miscellaneous Signals
Signal Name
Pin Number
I/O
Signal Description
DA
103
In
Reserved signal. This input must be connected to logic low.
INT
85
Out
Interrupt. INT is an open-drain output, driven low to indicate an interrupt. Once low, INT remains low until the
interrupt status in the appropriate interrupt Status Register is read. Interrupt sources are programmable via
the interrupt Mask Registers.
MM
6
In
Reserved signal. This input must be connected to logic low.
MODE[1:0]
7, 8
In
Mode Selects. They determine the configuration of the PHY/ATM interface. 00 = UTOPIA Level 2. 01 = UTO-
PIA Level 1. 10 = DPI. 11 is reserved.
OSC
126
In
TTL line rate clock source, driven by a 100 ppm oscillator. 32 MHz for 25.6 Mbps; 64 MHz for 51.2 Mbps.
RST
87
In
Reset. Active low asynchronous input resets all control logic, counters and FIFOs. A reset must be per-
formed after power up prior to normal operation of the part.
RXLED[3:0]
82, 81, 80, 79
Out
Receive LED drivers. Driven low for 223 cycles of OSC, beginning with RXSOC when that port receives a
good (non-null and non-errored) cell. Drives 8 mA both high and low. One per port.
RXREF
9
Out
Receive Reference. Active low, synchronous to OSC. RXREF pulses low for a programmable number of
clock cycles when an x_8 command byte is received. Register 0x40 is programmed to indicate which port is
referenced.
SE
102
In
Reserved signal. This input must be connected to logic low.
Table 1 Signal Descriptions (Part 1 of 3)
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