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參數(shù)資料
| 型號： | IDT82V2088BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | OCTAL CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PBGA208 |
| 封裝： | PLASTIC, BGA-208 |
| 文件頁數(shù)： | 59/375頁 |
| 文件大小： | 2430K |
| 代理商： | IDT82V2088BB |
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IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
48
October 7, 2003
3.14
ELASTIC STORE BUFFER
In Receive Clock Slave mode and Receive Multiplexed mode, a 2-
basic-frame depth Elastic Store Buffer is used to synchronize the incom-
ing frames to the (Multiplexed) Receive Side System Clock derived from
the RSCKn/MRSCK pin, and to the (Multiplexed) Receive Side System
Frame Pulse derived from the RSFSn/MRSFS pin. A write pointer is
used to write the data to the Elastic Store Buffer, while a read pointer is
used to read the data from the Elastic Store Buffer.
When the average frequency of the incoming data is greater than
the average frequency of the (Multiplexed) Receive Side System Clock
(RSCKn/MRSCK), the write pointer will be faster than the read pointer
and the Elastic Store Buffer will be filled. Until there is less than or equal
to 2 bytes between the write pointer and the read pointer, a frame will be
deleted after its prior frame is read. When the read pointer crosses the
frame boundary, a controlled slip will occur with a ‘1’ indicated in the
SLIPD bit.
When the average frequency of the incoming data is less than the
average frequency of the RSCKn/MRSCK, the write pointer will be
slower than the read pointer and the Elastic Store Buffer will be empty.
Until there is less than or equal to 2 bytes between the write pointer and
the read pointer, the frame will be repeated after it is read. When the
read pointer crosses the next frame boundary, a controlled slip will occur
with a ‘0’ indicated in the SLIPD bit.
When the slip occurs, the SLIPI bit will indicate it. An interrupt on
the
INT
pin will occur if the SLIPE bit is ‘1’.
In Receive Clock Slave mode and Receive Multiplexed mode, if it is
out of synchronization, the trunk code programmed in the TRK-
CODE[7:0] bits will be set to replace the data if the TRKEN bit is set to
‘1’.
In Receive Clock Master mode, the Elastic Store Buffer is
bypassed unless the device is in the Payload Loopback diagnosis mode
(refer to Chapter 3.27.2.2 Payload Loopback).
3.15
RECEIVE CAS/RBS BUFFER
The Receive CAS/RBS Buffer extracts the signaling bits from the
received data stream.
3.15.1
T1/J1 MODE
In SF/ESF/SLC-96 format, the signaling bits are located in the Bit 8
of Frame 6n (n = 1,2 in SF format; 1
≤
n
≤
4 in ESF format; 1
≤
n
≤
12 in
SLC-96 format) (refer to Table 12, Table 13 and Table 15 respectively).
The signaling codewords (AB or ABCD) are clocked out on the RSIG/
MRSIG pins. They are in the lower nibble of the channel with its corre-
sponding data serializing on the RSD/MRSD pins (as shown in
Figure 15).
When the EXTRACT bit is set to ‘1’, the signaling bits in its corre-
sponding channel are extracted to the A,B,C,D bits in the Extracted Sig-
naling Data/Extract Enable register. In SF format, the C,D bits in the
register are the repetition of the signaling bits A,B. The data in the
A,B,C,D bits in the Extracted Signaling Data/Extract Enable register are
the data to be output on the RSIG/MRSIG pins. However, in T1-DM for-
mat, there is no signaling bits.
Signaling de-bounce will be executed when the DEB bit is set to ‘1’.
Thus, the A,B,C,D bits in the Extracted Signaling Data/Extract Enable
register are updated only if 2 consecutive received AB/ABCD codewords
of the same channel are identical.
Signaling freezing is performed automatically when it is out of
frame synchronization or when slips occurs in the Elastic Store Buffer. It
is also performed when the FREEZE bit is set to ‘1’. The signaling freez-
ing freezes the signaling data in the A,B,C,D bits in the Extracted Signal-
ing Data/Extract Enable register as the previous valid value.
In the ESF and SLC-96 format, if the SIGF bit is set to ‘0’, the
extracted signaling bits are in 4 states signaling, i.e., the signaling bits
on Framer 6 & 18 of a signaling multi-frame are recognized as ‘A’ and
the signaling bits on Framer 12 & 24 are recognized as ‘B’. Only the sig-
naling bits A & B will be saved in the Extracted Signaling Data/Extract
Enable register, and the C & D bits in the Extracted Signaling Data/
Extract Enable register are Don’t-Care. If the SIGF bit is set to ‘1’, the
extracted signaling bits are in 16 states signaling, i.e., four signaling bits
A, B, C & D are all saved in the Extracted Signaling Data/Extract Enable
register.
Each time the extracted signaling bits stored in the Extracted Sig-
naling Data/Extract Enable register are changed, it is captured by the
corresponding COSI[X] bit (1
≤
X
≤
24). When the SIGE bit is set to ‘1’,
any one of the COSI[X] bits being ‘1’ will generate an interrupt and will
be reported by the
INT
pin.
The EXTRACT bit and the A,B,C,D bits are in the indirect registers
of the Receive CAS/RBS Buffer. They are accessed by specifying the
address in the ADDRESS[6:0] bits. Whether the data is read from or
written into the specified indirect register is determined by the RWN bit
and the data is in the D[7:0] bits. The access status is indicated in the
BUSY bit. Refer to Chapter 4.5 Indirect Register Access Scheme for
details about the indirect registers write/read access.
Table 34: Related Bit / Register In Chapter 3.14
Bit
Register
Address (Hex)
SLIPD
SLIPE
TRKEN
SLIPI
ELST Configuration
07C
ELST Interrupt Indication
ELST Trunk Code
07D
07E
TRKCODE[7:0]
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