- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377488 > IDT82V2088BB (INTEGRATED DEVICE TECHNOLOGY INC) OCTAL CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT82V2088BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | OCTAL CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PBGA208 |
| 封裝： | PLASTIC, BGA-208 |
| 文件頁數(shù)： | 64/375頁 |
| 文件大?。?/td> | 2430K |
| 代理商： | IDT82V2088BB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁當(dāng)前第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁第266頁第267頁第268頁第269頁第270頁第271頁第272頁第273頁第274頁第275頁第276頁第277頁第278頁第279頁第280頁第281頁第282頁第283頁第284頁第285頁第286頁第287頁第288頁第289頁第290頁第291頁第292頁第293頁第294頁第295頁第296頁第297頁第298頁第299頁第300頁第301頁第302頁第303頁第304頁第305頁第306頁第307頁第308頁第309頁第310頁第311頁第312頁第313頁第314頁第315頁第316頁第317頁第318頁第319頁第320頁第321頁第322頁第323頁第324頁第325頁第326頁第327頁第328頁第329頁第330頁第331頁第332頁第333頁第334頁第335頁第336頁第337頁第338頁第339頁第340頁第341頁第342頁第343頁第344頁第345頁第346頁第347頁第348頁第349頁第350頁第351頁第352頁第353頁第354頁第355頁第356頁第357頁第358頁第359頁第360頁第361頁第362頁第363頁第364頁第365頁第366頁第367頁第368頁第369頁第370頁第371頁第372頁第373頁第374頁第375頁
IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Functional Description
53
October 7, 2003
3.17
RECEIVE SYSTEM INTERFACE
The Receive System Interface determines how to output the
received data stream to the system backplane. The timing clocks and
framing pulses can be provided by the system backplane or obtained
from the far end. The Receive System Interface supports various config-
urations to meet various requirements in different applications.
3.17.1
T1/J1 MODE
In T1/J1 mode, the Receive System Interface can be set in Non-
multiplexed Mode or Multiplexed Mode. In the Non-multiplexed Mode,
the RSD pin is used to output the received data at the bit rate of 1.544
Mb/s or 2.048 Mb/s (T1/J1 mode E1 rate). While in the Multiplexed
Mode, the received data from the link is converted to 2.048 Mb/s format
and byte interleaved to form one high speed data stream and output on
the MRSD pin at the bit rate of 8.192 Mb/s.
In the Non-multiplexed Mode, if the receive system interface and
the receive line side are timed to a same clock source, the Receive Sys-
tem Interface is in Receive Clock Master mode. If the receive system
interface and the receive line side are timed to different clock sources,
the Receive System Interface is in Receive Clock Slave mode.
In the Receive Clock Master mode, if RSCK outputs pulses during
the entire T1/J1 frame, the Receive System Interface is in Receive Clock
Master Full T1/J1 mode. If only the clocks aligned to the selected chan-
nels are output on RSCK, the Receive System Interface is in Receive
Clock Master Fractional T1/J1 mode.
In the Receive Clock Slave mode, the backplane data rate may be
equal to 1.544 Mb/s (i.e., the line data rate) or 2.048 Mb/s. If the back-
plane data rate is 2.048 Mb/s, the Receive System Interface is in T1/J1
mode E1 rate and the received data stream (1.544 Mb/s) should be
mapped per 3 kinds of schemes.
In the Receive Multiplexed mode, since the received data should
be converted to 2.048 Mb/s format first and then multiplexed to 8.192
Mb/s, there are still 3 kinds of schemes to be selected.
Table 39 summarizes how to set the Receive System Interface into
various operating modes and the pins’ direction of the Receive System
Interface in different operating modes.
3.17.1.1
Receive Clock Master Mode
In the Receive Clock Master mode, the timing signal on the RSCK
pin and framing pulse on the RSFS pin are used to output the data on
the RSD pin. The signaling bits on the RSIG pin are per-channel aligned
with the data on the RSD pin.
In the Receive Clock Master mode, the data on the system inter-
face is clocked by the RSCK. The active edge of the RSCK used to
update the pulse on the RSFS is determined by the FE bit. The active
edge of the RSCK used to update the data on the RSD and RSIG is
determined by the DE bit. If the FE bit and the DE bit are not equal, the
pulse on the RSFS is ahead.
In the Receive Clock Master mode, the RSFS can indicate each F-
bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. In SF
format, the RSFS can also indicate every second F-bit or the first F-bit of
every second SF multi-frame. All the indications are selected by the
CMFS bit and the ALTIFS bit. The active polarity of the RSFS is selected
by the FSINV bit.
The Receive Clock Master mode includes two sub-modes: Receive
Clock Master Full T1/J1 mode and Receive Clock Master Fractional T1/
J1 mode.
3.17.1.1.1
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCK is a
standard 1.544 MHz clock, and the data in the F-bit and all 24 channels
in a standard T1/J1 frame are clocked out by the RSCK.
Receive Clock Master Full T1/J1 Mode
3.17.1.1.2
Besides all the common functions described in the Receive Clock
Master mode, the special feature in this mode is that the RSCK is a
gapped 1.544 MHz clock (no clock signal during the selected position).
Receive Clock Master Fractional T1/J1 Mode
Table 39: Operating Modes Selection In T1/J1 Receive Path
RMUX RMODE
G56K, GAP /
FBITGAP
MAP[1:0]
2
Operating Mode
Receive System Interface Pin
Input
Output
0
0
00 / 0
not all 0s
1
X
Receive Clock Master Full T1/J1
Receive Clock Master Fractional T1/J1
X
RSCK, RSFS,
RSD, RSIG
1
X
00
01
10
11
01
10
11
Receive Clock Slave - T1/J1 Rate
Receive Clock Slave - T1/J1 Mode E1 Rate per G.802
Receive Clock Slave - T1/J1 Mode E1 Rate per One Filler Every Four CHs
Receive Clock Slave - T1/J1 Mode E1 Rate per Continuous CHs
Receive Multiplexed - T1/J1 Mode E1 Rate per G.802
Receive Multiplexed - T1/J1 Mode E1 Rate per One Filler Every Four CHs
Receive Multiplexed - T1/J1 Mode E1 Rate per Continuous CHs
RSCK, RSFS
RSD, RSIG
1
X
X
MRSCK, MRSFS
MRSD, MRSIG
NOTE:
1. When the G56K, GAP bits in RPLC indirect registers are set, the PCCE bit must be set to ‘1’.
2. The MAP[1:0] bits can not be set to ‘00’ in the Receive Multiplexed mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT82V2058DA | OCTAL E1 SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2608BB | INVERSE MULTIPLEXING FOR ATM |
| IDT82V2608 | INVERSE MULTIPLEXING FOR ATM |
| IDT82V3001A | WAN PLL WITH SINGLE REFERENCE INPUT |
| IDT82V3001APV | WAN PLL WITH SINGLE REFERENCE INPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V2088BBG | 功能描述:IC LINE INTERFACE UNIT 208-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2088DR | 功能描述:IC LIU T1/J1/E1 8CH 208-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2088DRG | 功能描述:IC LIU T1/J1/E1 8CH 208-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2108 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:T1 / E1 / J1 OCTAL FRAMER |
| IDT82V2108BB | 功能描述:IC FRAMER T1/J1/E1 8CH 144-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。