- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄11568 > IDT82V2108PX (IDT, Integrated Device Technology Inc)IC FRAMER T1/J1/E1 8CH 128-PQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT82V2108PX |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 285/292頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FRAMER T1/J1/E1 8CH 128-PQFP |
| 標(biāo)準(zhǔn)包裝： | 11 |
| 控制器類(lèi)型： | T1/E1/J1 調(diào)幀器 |
| 接口： | 并聯(lián) |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 電流 - 電源： | 160mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-PQFP（14x20） |
| 包裝： | 托盤(pán) |
| 其它名稱(chēng)： | 82V2108PX |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)當(dāng)前第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)
IDT82V2108
T1 / E1 / J1 OCTAL FRAMER
Functional Description
82
March 5, 2009
3.16
HDLC TRANSMITTER (THDLC)
The HDLC data insertion is performed in this block. The HDLC
Transmitters #1, #2 and #3 in E1 mode or the HDLC Transmitter #1 and
#2 in T1/J1 mode ESF format of each framer operate independently.
3.16.1
E1 MODE
Three HDLC Transmitter blocks are provided for each framer to
transmit a HDLC link. Before selecting the HDLC link, the TXCISEL (b3,
E1-0AH) should be set to ‘1’. Thus, the configuration of Link Control and
Bits Select registers (addressed from 028H to 02DH) is for THDLC. The
THDLCSEL[1:0] (b5~4, E1-00AH) select one of the three HDLC control-
lers to be accessed by the microcontroller. The #2 and #3 blocks can
also be disabled by setting the V52DIS (b3, E1-007H). The functionality
of the HDLC link can be defined as the follows:
1. Set the DL_EVEN (b7, E1-028H or b7, E1-02AH or b7, E1-
02CH) and/or the DL_ODD (b6, E1-028H or b6, E1-02AH or b6, E1-
02CH) to select the even and/or odd frames (the even frames are FAS
frames while the odd frames are NFAS frames);
2. Set the DL_TS[4:0] (b4~0, E1-028H or b4~0, E1-02AH or b4~0,
E1-02CH) to select the time slot of the assigned frame or to set the
TS16_EN (b5, E1-028H) to define TS16 of the assigned frame (this
HDLC link can only be set in the #1 block and is enabled when the CCS
is selected by the SIGEN [b6, E1-040H] and the DLEN [b5, E1-040H]);
3. Set the DL_BIT[7:0] (b7~0, E1-029H or b7~0, E1-02BH or b7~0,
E1-02DH) to select the bit of the assigned time slot.
Thereafter, the HDLC packet will replace the data on the assigned
data link. All the functions of the selected HDLC Transmitter block are
realized only if the EN (b0, E1-050H) is set to logic 1; otherwise, all ones
will be transmitted on the assigned data link.
A normal HDLC packet (refer to Figure 5) is started with a 7E (Hex)
flag, then the HDLC data is transmitted. Before closing, two bytes of
CRC-CCITT frame check sequences (FCS) are added if the CRC (b1,
E1-050H) is enabled. The HDLC packet is closed with another 7E flag.
However, if the FLGSHARE (b7, E1-050H) is set, the closing flag of the
current HDLC packet and the opening flag of the next HDLC packet are
shared.
A FIFO buffer is used to store the HDLC data written to the TD[7:0]
(b7~0, E1-055H). The UTHR[6:0] (b6~0, E1-051H) set the upper thresh-
old of the FIFO. When the data exceeds the fill level, the data will be
transmitted. The opening flag will be prepended before the data auto-
matically. The transmission will not stop until the entire HDLC data is
transmitted and the data in the FIFO is below the upper threshold. The
end of the current entire HDLC frame is set by the EOM (b3, E1-050H).
When it is set, the HDLC data should be transmitted even if it does not
exceed the upper threshold of the FIFO. The FCS, if enabled, will be
added before the closing flag automatically. Zero stuffing is automatically
performed to the serial output data when there are five consecutive ones
in the HDLC data or in the FCS. A 7F (Hex) abort sequence which deac-
tivates the current HDLC packet can be inserted anytime the ABT (b2,
E1-050H) is set. When the ABT (b2, E1-050H) is set, the current byte in
the TD[7:0] (b7~0, E1-055H) is still transmitted, and then the FIFO is
cleared and the 7F abort sequence is transmitted continuously. The low
threshold of the FIFO can be set in the LINT[6:0] (b6~0, E1-052H),
which should always be less than the value of the UTHR[6:0] (b6~0, E1-
051H). The FIFO can be cleared anytime the FIFOCLR (b6, E1-050H) is
set. Flags (7E) will consecutively be transmitted when there is no HDLC
data to be transmitted if the data link is activated.
Four interrupt sources can be derived from this block.
1. When the data in the FIFO is empty or less than the setting in the
LINT[6:0] (b6~0, E1-052H), the BLFILL (b5, E1-054H) will indicate. A
transition from logic 0 to 1 on the BLFILL (b5, E1-054H) will cause a
logic 1 in the LFILLI (b0, E1-054H). The interrupt on the INT pin will
occur when the LFILLE (b0, E1-053H) is enabled;
2. When the data in the FIFO reaches its maximum capacity - 128
bytes, the FULL (b6, E1-054H) will be set for indication. A transition from
logic 0 to 1 on the FULL (b6, E1-054H) will cause a logic 1 in the FULLI
(b3, E1-054H). The interrupt on the INT pin will occur when the FULLE
(b3, E1-053H) is enabled;
3. When the FIFO has already been filled with 128 bytes and new
data is still written to it, the FIFO will overflow and the OVRI (b2, E1-
054H) will be set for indication. The interrupt on the INT pin will occur
when the OVRE (b2, E1-053H) is enabled.
4. When the transmission is in process and it is out of data to be
transmitted in the FIFO, the FIFO is underrun and the UDRI (b1, E1-
054H) will be set for indication. The interrupt on the INT pin will occur
when the UDRE (b1, E1-053H) is enabled.
3.16.2
T1/J1 MODE
In the SF format, there is no HDLC link.
In the ESF format, two HDLC Transmitter blocks (#1 and #2) are
employed for each framer to transmit the HDLC link. Before selecting
the HDLC link, the TXCISEL (b3, T1/J1-00DH) should be set to ‘1’.
Thus, the configuration of the Link Control and Bits Select registers
(addressed from 070H to 071H) is for THDLC. Selected by the
THDLCSEL[1:0] (b5~4, T1/J1-00DH), registers in one of the two HDLC
Transmitter blocks are accessible to the microprocessor. The #1 block
transmits the HDLC link in the DL of F-bit (its position is shown in the
Table 4). The #2 block transmits the HDLC link in a channel and its posi-
tion is selected as follows:
1. Set the DL2_EVEN (b7, T1/J1-070H) and/or the DL2_ODD (b6,
T1/J1-070H) to select the even and/or odd frames;
2. Set the DL2_TS[4:0] (b4~0, T1/J1-070H) to select the channel of
the assigned frame;
3. Set the DL2_BIT[7:0] (b7~0, T1/J1-071H) to select the bit of the
assigned channel.
All the functions of the selected HDLC Transmitter block are real-
ized only if the EN (b0, T1/J1-034H) is enabled; otherwise, all ones will
be transmitted on the assigned data link.
The structure of the HDLC packet (refer to Figure 5) is the same as
it is described in the E1 mode. When the FLGSHARE (b7, T1/J1-034H)
is set, the closing flag of the current HDLC and the opening flag of the
next HDLC are shared.
A FIFO buffer is used to store the HDLC data written to the TD[7:0]
(b7~0, T1/J1-039H). The UTHR[6:0] (b6~0, T1/J1-035H) limit the upper
threshold of the FIFO. When the data exceeds the fill level, the data will
be transmitted. The opening flag will be added before the data automati-
cally. The transmission will not stop until an entire HDLC frame is trans-
mitted and the data in the FIFO is below the upper threshold. The end of
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-2TP-IX-S | CONVERTER MOD DC/DC 13.8V 75W |
| VE-2TN-IX-S | CONVERTER MOD DC/DC 18.5V 75W |
| PIC16LF1904-E/P | MCU 7KB FLASH 256B RAM 40PDIP |
| IDT82V2108PXG8 | IC FRAMER T1/J1/E1 8CH 128-PQFP |
| IDT82V2108PX8 | IC FRAMER T1/J1/E1 8CH 128-PQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V2108PX8 | 功能描述:IC FRAMER T1/J1/E1 8CH 128-PQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類(lèi)型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱(chēng):Q6396337A |
| IDT82V2108PXG | 功能描述:IC FRAMER T1/J1/E1 8CH 128-PQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類(lèi)型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱(chēng):Q6396337A |
| IDT82V2108PXG8 | 功能描述:IC FRAMER T1/J1/E1 8CH 128-PQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類(lèi)型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱(chēng):Q6396337A |
| IDT82V2604 | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:INVERSE MULTIPLEXING FOR ATM IDT82V2604 |
| IDT82V2604BB | 功能描述:IC INVERSE MUX 4CH ATM 208-BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤(pán)（4x4） 包裝:帶卷 (TR) 安裝類(lèi)型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱(chēng):296-25223-2 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。