參數(shù)資料
型號(hào): IDT82V3010
廠商: Integrated Device Technology, Inc.
英文描述: T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS
中文描述: T1/E1/OC3電信時(shí)鐘發(fā)生器,雙基準(zhǔn)輸入
文件頁(yè)數(shù): 26/31頁(yè)
文件大?。?/td> 355K
代理商: IDT82V3010
IDT82V3010
T1/E1/OC3 Telecom Clock Generator with Dual Reference Inputs
Timing Characteristics
26
June 19, 2006
8
TIMING CHARACTERISTICS
8.1
TIMING PARAMETER MEASUREMENT VOLTAGE LEVELS
Figure - 11 Timing Parameter Measurement Voltage Levels
Notes:
1. Voltages are with respect to ground (V
SS
) unless otherwise stated.
2. Supply voltage and operating temperature are as per Recommended Operating Conditions.
3. Timing for input and output signals is based on the worst case result of the CMOS thresholds.
8.2
INPUT/OUTPUT TIMING
Parameter
Description
CMOS
Units
V
T
Threshold Voltage
0.5V
DDD
V
V
HM
Rise and Fall Threshold Voltage High
0.7V
DDD
V
V
LM
Rise and Fall Threshold Voltage Low
0.3V
DDD
V
Parameter
Description
Min.
Typ.
Max.
Units
Test Conditions
8 kHz, 1.544 MHz or 2.048 MHz
reference input
19.44 MHz reference input
t
RW
Reference input pulse width high or low
51
ns
5
ns
t
IRF
Reference input rise or fall time
10
ns
t
R8D
8 kHz reference input to F8o delay
8
ns
t
R15D
1.544 MHz reference input to F8o delay
332
ns
t
R2D
2.048 MHz reference input to F8o delay
253
ns
t
R19D
19.44 MHz reference input to F8o delay
8
ns
t
F0D
F8o to
F0o
delay
118
121
124
ns
t
F16S
F16o
setup to
C16o
falling
25
40
ns
t
F16H
F16o
hold to
C16o
falling
25
40
ns
t
F19S
F19o setup to C19o falling
20
35
ns
t
F19H
F19o hold to C19o falling
20
35
ns
t
C15D
F8o to C1.5o delay
-3
0
+3
ns
t
C3D
F8o to
C3o
delay
-3
1.6
+3
ns
t
C6D
F8o to C6o delay
-3
1.6
+3
ns
t
C2D
F8o to C2o
-2
0
+2
ns
t
C4D
F8o to
C4o
-2
0
+2
ns
t
C8D
F8o to C8o delay
-2
0
+2
ns
t
C16D
F8o to
C16o
delay
-2
0
+2
ns
Timing Reference Points
t
IRF,
t
ORF
t
IRF,
t
ORF
V
HM
V
T
V
LM
All Siganls
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