參數(shù)資料
型號: IDT82V3280DQG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 50/171頁
文件大?。?/td> 0K
描述: IC PLL WAN SE STRATUM 2 100-TQFP
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 14:9
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 托盤
其它名稱: 82V3280DQG
IDT82V3280
WAN PLL
Programming Information
143
December 9, 2008
OUT8_FREQ_CNFG - Output Clock 8 Frequency Configuration & Output Clock 6, 7 & 9 Invert Configuration
Address:72H
Type: Read / Write
Default Value: 01000000
Bit
Name
Description
7
OUT8_PATH_SEL
These bits select an input to OUT8.
0: The output of T4 DPLL 77.76 MHz path. (default)
1: The output of T0 DPLL 77.76 MHz path.
6
OUT8_EN
Refer to the description of the T4_INPUT_FAIL bit (b5, 72H).
5
T4_INPUT_FAIL
This bit, together with the OUT8_EN bit (b6, 72H), determines whether a clock is enabled to be output on OUT8.
4
AMI_OUT_DUTY
This bit determines the duty cycle of the output on OUT8.
0: 50:50. (default)
1: 5:8.
3
400HZ_SEL
This bit determines the frequency of the output on OUT8.
0: 64 kHz + 8 kHz. (default)
1: 64 kHz + 8 kHz + 0.4 kHz.
2OUT9_INV
This bit determines whether the output on OUT9 is inverted.
0: Not inverted. (default)
1: Inverted.
1OUT7_INV
This bit determines whether the output on OUT7 is inverted.
0: Not inverted. (default)
1: Inverted.
0OUT6_INV
This bit determines whether the output on OUT6 is inverted.
0: Not inverted. (default)
1: Inverted.
76543210
OUT8_PATH_S
EL
OUT8_EN
T4_INPUT_FAI
L
AMI_OUT_DUT
Y
400HZ_SEL
OUT9_INV
OUT7_INV
OUT6_INV
OUT8_EN T4_INPUT_FAIL
Output on OUT8
0
don’t-care
Output is disabled (output low).
1
0
Output is enabled. (default)
1
Output is enabled when the T4 selected input clock does not fail.
Output is disabled (output low) when the T4 selected input clock fails.
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