![](http://datasheet.mmic.net.cn/330000/IDT82V3288_datasheet_16416018/IDT82V3288_14.png)
IDT82V3288
WAN PLL
Pin Description
14
June 22, 2006
RST
A14
I
pull-up
CMOS
RST
: Reset
A low pulse of at least 50 μs on this pin resets the device. After this pin is high, the device will
still be held in reset state for 500 ms (typical).
Frame Synchronization Input Signal
EX_SYNC1
N16
I
pull-down
I
pull-down
I
pull-down
CMOS
EX_SYNC1: External Sync Input 1
A 2 kHz, 4 kHz or 8 kHz signal is input on this pin.
EX_SYNC2: External Sync Input 2
A 2 kHz, 4 kHz or 8 kHz signal is input on this pin.
EX_SYNC3: External Sync Input 3
A 2 kHz, 4 kHz or 8 kHz signal is input on this pin.
EX_SYNC2
K15
CMOS
EX_SYNC3
H15
CMOS
Input Clock
IN1
R1
I
AMI
IN1: Input Clock 1
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin.
IN2: Input Clock 2
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin.
IN3: Input Clock 3
A 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN4: Input Clock 4
A 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN5_POS / IN5_NEG: Positive / Negative Input Clock 5
A 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz
clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is
automatically detected.
IN6_POS / IN6_NEG: Positive / Negative Input Clock 6
A 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz
clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is
automatically detected.
IN7: Input Clock 7
A 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN8: Input Clock 8
A 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN9: Input Clock 9
A 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN10: Input Clock 10
A 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
IN11: Input Clock 11
A 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz,
25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin.
In Slave operation, the frequency of the T0 selected input clock IN11 is recommended to be
6.48 MHz.
IN2
R2
I
AMI
IN3
N14
I
pull-down
CMOS
IN4
M15
I
pull-down
CMOS
IN5_POS
IN5_NEG
T15
T16
I
PECL/LVDS
IN6_POS
IN6_NEG
P15
P16
I
PECL/LVDS
IN7
L16
I
pull-down
CMOS
IN8
L14
I
pull-down
CMOS
IN9
J16
I
pull-down
CMOS
IN10
J14
I
pull-down
CMOS
IN11
G16
I
pull-down
CMOS
Table 1: Pin Description (Continued)
Name
Pin No.
I/O
Type
Description
1