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參數(shù)資料
| 型號： | IDT82V3288 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | WAN PLL |
| 中文描述： | 廣域網(wǎng)鎖相環(huán) |
| 文件頁數(shù)： | 6/170頁 |
| 文件大?。?/td> | 1053K |
| 代理商： | IDT82V3288 |
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List of Tables
6
June 22, 2006
Table 1: Pin Description ............................................................................................................................................................................................. 13
Table 2: Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 20
Table 3: Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 21
Table 4: Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 23
Table 5: Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 25
Table 6: Input Clock Selection for T0 Path ................................................................................................................................................................ 26
Table 7: Input Clock Selection for T4 Path ................................................................................................................................................................ 26
Table 8: External Fast Selection ................................................................................................................................................................................ 26
Table 9: Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 27
Table 10: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 28
Table 11: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 28
Table 12: Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 29
Table 13: Conditions of Qualified Input Clocks Available for T0 & T4 Selection ......................................................................................................... 30
Table 14: Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 31
Table 15: T0 DPLL Operating Mode Control ............................................................................................................................................................... 32
Table 16: T4 DPLL Operating Mode Control ............................................................................................................................................................... 34
Table 17: Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 34
Table 18: Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 35
Table 19: Frequency Offset Control in Holdover Mode ............................................................................................................................................... 36
Table 20: Holdover Frequency Offset Read ................................................................................................................................................................ 36
Table 21: Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 37
Table 22: Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 39
Table 23: Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 40
Table 24: Outputs on OUT1 ~ OUT7 if Derived from T0/T4 DPLL Outputs ................................................................................................................ 41
Table 25: Outputs on OUT1 ~ OUT7 if Derived from T0/T4 APLL .............................................................................................................................. 42
Table 26: Outputs on OUT8 & OUT9 ........................................................................................................................................................................... 42
Table 27: Frame Sync Input Signal Selection .............................................................................................................................................................. 43
Table 28: Synchronization Control ............................................................................................................................................................................... 43
Table 29: Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 44
Table 30: Device Master / Slave Control ..................................................................................................................................................................... 45
Table 31: Related Bit / Register in Chapter 3.15 ......................................................................................................................................................... 46
Table 32: Microprocessor Interface ............................................................................................................................................................................. 50
Table 33: Access Timing Characteristics in EPROM Mode ......................................................................................................................................... 51
Table 34: Read Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 52
Table 35: Write Timing Characteristics in Multiplexed Mode ....................................................................................................................................... 53
Table 36: Read Timing Characteristics in Intel Mode .................................................................................................................................................. 54
Table 37: Write Timing Characteristics in Intel Mode .................................................................................................................................................. 55
Table 38: Read Timing Characteristics in Motorola Mode ........................................................................................................................................... 56
Table 39: Write Timing Characteristics in Motorola Mode ........................................................................................................................................... 57
Table 40: Read Timing Characteristics in Serial Mode ................................................................................................................................................ 58
Table 41: Write Timing Characteristics in Serial Mode ................................................................................................................................................ 59
Table 42: JTAG Timing Characteristics ....................................................................................................................................................................... 60
Table 43: Register List and Map .................................................................................................................................................................................. 61
Table 44: Power Consumption and Maximum Junction Temperature ....................................................................................................................... 152
Table 45: Thermal Data ............................................................................................................................................................................................. 152
Table 46: Absolute Maximum Rating ......................................................................................................................................................................... 153
Table 47: Recommended Operation Conditions ........................................................................................................................................................ 153
Table 48: AMI Input / Output Port Electrical Characteristics ...................................................................................................................................... 155
List of Tables
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3288BC | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3288BCG | 功能描述:IC PLL WAN 3E STRATUM 2 208CABGA RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3352 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SYNCHRONOUS ETHERNET WAN PLL |
| IDT82V3355 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SYNCHRONOUS ETHERNET WAN PLL |
| IDT82V3355DKG | 功能描述:IC PLL WAN SYNC ETH 64-TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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