參數(shù)資料
型號(hào): IDT82V3288BC
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: WAN PLL
中文描述: SPECIALTY TELECOM CIRCUIT, PBGA208
封裝: PLASTIC, CABGA-208
文件頁數(shù): 17/170頁
文件大?。?/td> 1053K
代理商: IDT82V3288BC
IDT82V3288
WAN PLL
Pin Description
17
June 22, 2006
AD0 / SDO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
B10
A11
C9
A12
B11
C10
A13
B12
I/O
pull-down
CMOS
AD[7:0]: Address / Data Bus
In EPROM, Intel and Motorola modes, these pins are the bi-directional data bus of the micro-
processor interface.
In Multiplexed mode, these pins are the bi-directional address/data bus of the microproces-
sor interface.
SDO: Serial Data Output
In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked
out of the device on the active edge of SCLK.
In Serial mode, AD[7:1] pins should be connected to ground.
WR
A15
I
pull-up
CMOS
WR
: Write Operation
In Multiplexed and Intel modes, this pin is asserted low to initiate a write operation.
In Motorola mode, this pin is asserted low to initiate a write operation or s asserted high to ini-
tiate a read operation.
In EPROM and Serial modes, this pin should be connected to ground.
RD
C12
I
pull-up
CMOS
RD
: Read Operation
In Multiplexed and Intel modes, this pin is asserted low to initiate a read operation.
In EPROM, Motorola and Serial modes, this pin should be connected to ground.
ALE: Address Latch Enable
In Multiplexed mode, the address on AD[7:0] pins is sampled into the device on the falling
edge of ALE.
ALE / SCLK
B13
I
pull-down
CMOS
SCLK: Shift Clock
In Serial mode, a shift clock is input on this pin.
Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated
on the active edge of SCLK. The active edge is determined by the CLKE.
In EPROM, Intel and Motorola modes, this pin should be connected to ground.
RDY: Ready/Data Acknowledge
In Multiplexed and Intel modes, a high level on this pin indicates that a read/write cycle is
completed. A low level on this pin indicates that wait state must be inserted.
In Motorola mode, a low level on this pin indicates that valid information on the data bus is
ready for a read operation or acknowledges the acceptance of the written data during a write
operation.
In EPROM and Serial modes, this pin should be connected to ground.
RDY
C11
O
CMOS
JTAG (per IEEE 1149.1)
TRST
C1
I
pull-down
CMOS
TRST
: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely
retain their state.
TMS
F1
I
pull-up
CMOS
TCK
E3
I
pull-down
CMOS
Table 1: Pin Description (Continued)
Name
Pin No.
I/O
Type
Description
1
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