參數(shù)資料
型號： IDT82V3288BCG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： WAN PLL
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA208
封裝： GREEN, PLASTIC, CABGA-208
文件頁數(shù)： 13/170頁
文件大小： 1053K
代理商： IDT82V3288BCG
IDT82V3288
WAN PLL
Pin Description
13
June 22, 2006
2
PIN DESCRIPTION
Table 1: Pin Description
Name
Pin No.
I/O
Type
Description
1
Global Control Signal
BOS_MODE0
R16
I
CMOS
BOS_MODE0: Function Application Control
The device supports two applications, as controlled by this pin:
High: Master / Slave application;
Low: Line Card application.
Refer to
Chapter 4 Typical Application
for details.
OSCI: Crystal Oscillator Master Clock
A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the
master clock for the device.
OSCI_MON: Crystal Oscillator Master Clock Monitoring
A 12.8 MHz clock is input on this pin to monitor the master clock.
Refer to
Chapter 3.2 Master Clock & Master Clock Monitoring
for details.
T0_LPF: T0 APLL External RC (Resistor-Capacitor) Filter Connection
This pin connects an external RC filter to GND.
T4_LPF: T4 APLL External RC (Resistor-Capacitor) Filter Connection
This pin connects an external RC filter to GND.
T0_LOCK: T0 DPLL Phase Locking Status Indication
This pin indicates the T0 DPLL phase locking status.
When the T0 DPLL is phase locked to the T0 selected input clock, this pin is high; otherwise,
it is low.
This pin corresponds to the status indication in the T0_DPLL_LOCK bit (b3, 52H)
2
.
T4_LOCK: T4 DPLL Phase Locking Status Indication
This pin indicates the T4 DPLL phase locking status.
When the T4 DPLL is phase locked to the T4 selected input clock, this pin is high; otherwise,
it is low.
This pin corresponds to the status indication by the T4_DPLL_LOCK bit (b6, 52H).
FF_SRCSW: External Fast Selection Enable
During reset, this pin determines the default value of the EXT_SW bit (b4, 0BH)
2
. The
EXT_SW bit determines whether the External Fast Selection is enabled.
High: The default value of the EXT_SW bit (b4, 0BH) is ‘1’ (External Fast selection is
enabled);
Low: The default value of the EXT_SW bit (b4, 0BH) is ‘0’ (External Fast selection is dis-
abled).
After reset, this pin selects an input clock pair for the T0 DPLL if the External Fast selection is
enabled:
High: Pair IN3 / IN5 is selected.
Low: Pair IN4 / IN6 is selected.
After reset, the input on this pin takes no effect if the External Fast selection is disabled.
OSCI
G1
I
CMOS
OSCI_MON
A1
I
pull-down
CMOS
T0_LPF
J3
O
CMOS
T4_LPF
D3
O
CMOS
T0_LOCK
E14
O
CMOS
T4_LOCK
E15
O
CMOS
FF_SRCSW
K1
I
pull-down
CMOS
MS/
SL
C3
I
pull-up
CMOS
MS/
SL
: Master / Slave Selection
This pin, together with the MS_SL_CTRL bit (b0, 13H), controls whether the device is config-
ured as the Master or as the Slave. Refer to
Chapter 3.14 Master / Slave Configuration
for
details.
The signal level on this pin is reflected by the MASTER_SLAVE bit (b1, 09H).
SONET/
SDH
B2
I
pull-down
CMOS
SONET/
SDH
: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
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