參數(shù)資料
型號: IDT82V3288BCG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: WAN PLL
中文描述: SPECIALTY TELECOM CIRCUIT, PBGA208
封裝: GREEN, PLASTIC, CABGA-208
文件頁數(shù): 70/170頁
文件大?。?/td> 1053K
代理商: IDT82V3288BCG
IDT82V3288
WAN PLL
Programming Information
70
June 22, 2006
PHASE_ALARM_TIME_OUT_CNFG - Phase Lock Alarm Time-Out Configuration
Address: 08H
Type: Read / Write
Default Value: 00110010
Bit
Name
Description
7 - 6
MULTI_FACTOR[1:0]
These bits determine a factor which has a relationship with a period in seconds. A phase lock alarm will be raised if the T0
selected input clock is not locked in T0 DPLL within this period. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the
phase lock alarm will be cleared after this period (starting from when the alarm is raised). Refer to the description of the
TIME_OUT_VALUE[5:0] bits (b5~0, 08H).
00: 2 (default)
01: 4
10: 8
11: 16
These bits represent an unsigned integer. If the value in these bits is multiplied by the value in the MULTI_FACTOR[1:0]
bits (b7~6, 08H), a period in seconds will be gotten.
A phase lock alarm will be raised if the T0 selected input clock is not locked in T0 DPLL within this period. If the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the phase lock alarm will be cleared after this period (starting from when the
alarm is raised).
5 - 0
TIME_OUT_VALUE[5:0]
7
6
5
4
3
2
1
0
MULTI_FACTO
R1
MULTI_FACTO
R0
TIME_OUT_VA
LUE5
TIME_OUT_VA
LUE4
TIME_OUT_VA
LUE3
TIME_OUT_VA
LUE2
TIME_OUT_VA
LUE1
TIME_OUT_VAL
UE0
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