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參數(shù)資料
| 型號： | IDT85304-01PGGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 85304 SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | GREEN, TSSOP-20 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 89K |
| 代理商： | IDT85304-01PGGI8 |
8
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE-ENDED LEVELS
The diagram below shows how the differential input can be wired to accept single-ended levels. The reference voltage VREF
VDD/2isgeneratedbythe
bias resistors R1, R2, and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to
position the VREF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, VREF should be 1.25V and R2/
R1 = 0.609.
Single-Ended Signal Driving Differential Input
VDD
VREF
+
-
C1
0.1uF
CLK_IN
R1
1K
R2
1K
TERMINATION FOR LVPECL OUTPUTS
TheclocklayouttopologyshownbelowisatypicalterminationforLVPECLoutputs. Thetwodifferentlayoutsmentionedarerecommendedonlyasguidelines.
FOUT and xFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to
ground) or current sources must be used for functionality. These outputs are designed to drive 50
Ωtransmissionlines. Matchedimpedancetechniquesshould
be used to maximize operating frequency and minimize signal distortion. The diagrams below show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist. It is recommended that the board designers simulate to guarantee compatibility across all printed circuit and
clock component process variations.
LVPECL Output Termination, layout A
LVPECL Output Termination, layout B
FOUT
50
Ω
50
Ω
Zo = 50
Ω
VDD - 2V
Zo = 50
Ω
RTT
FIN
RTT =
(VOH + VOL / VDD - 2) - 2
1
Zo
FOUT
Zo = 50
Ω
Zo = 50
Ω
FIN
Zo
3
2
Zo
3
2
Zo
5
2
Zo
5
2
3.3V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT8535-01 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER |
| IDT8535-01PG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER |
| IDT8535-01PGG | 功能描述:IC CLOCK BUFFER MUX 2:4 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:- 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| IDT8535-01PGG8 | 功能描述:IC CLOCK BUFFER MUX 2:4 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:- 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| IDT8535-01PGGI | 功能描述:IC CLOCK BUFFER MUX 2:4 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:- 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
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