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參數(shù)資料
| 型號： | IDT85304-01PGGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 85304 SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | GREEN, TSSOP-20 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 89K |
| 代理商： | IDT85304-01PGGI8 |
2
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PIN CONFIGURATION
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
Unit
VDD
Power Supply Voltage
4.6
V
VI
Input Voltage
–0.5 to VDD+0.5
V
VO
Output Voltage
–0.5 to VDD+0.5
V
θJA
Package Thermal Impedance (0 lfpm)
92.6
°C/W
TSTG
Storage Temperature
–65 to +150
° C
CAPACITANCE(TA=+25°C,f=1MHz,V
IN
= 0V)
Parameter
Description
Typ.
Max.
Unit
CIN
InputCapacitance
—
4
pF
RPULLUP
Input Pullup Resistor
51
—
K
Ω
RPULLDOWN
Input Pulldown Resistor
51
—
K
Ω
TSSOP
TOP VIEW
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
xQ0
Q1
xQ1
Q2
xQ2
Q3
xQ3
Q4
xQ4
VDD
CLK_EN
VDD
xPCLK
PCLK
VEE
xCLK
CLK
CLK_SEL
VDD
PIN DESCRIPTION(1)
Symbol
Number
Type
Description
xQ0, Q0
1, 2
Output
Differential Output Pair. LVPECL interface levels.
xQ1, Q1
3, 4
Output
Differential Output Pair. LVPECL interface levels.
xQ2, Q2
5, 6
Output
Differential Output Pair. LVPECL interface levels.
xQ3, Q3
7, 8
Output
Differential Output Pair. LVPECL interface levels.
xQ4, Q4
9, 10
Output
Differential Output Pair. LVPECL interface levels.
VDD
11, 18, 20
Power
Positive Supply Pins
CLK_SEL
12
Input
Pulldown
Clock Select Input. When HIGH, selects PCLK / xPCLK inputs. When LOW, selects
CLK / xCLK inputs. LVTTL / LVCMOS interface levels.
CLK
13
Input
Pulldown
Non-Inverting Differential Clock Input
xCLK
14
Input
Pullup
Inverting Differential Clock Input
VEE
15
Power
Negative Supply Pin
PCLK
16
Input
Pulldown
Non-Inverting Differential LVPECL Clock Input
xPCLK
17
Input
Pullup
Inverting Differential LVPECL Clock Input
CLK_EN
19
Input
Pullup
Synchronizing Clock Enable. When HIGH, clock outputs follow clock input. When
LOW, Q outputs are forced LOW, xQ outputs are forced HIGH. LVTTL / LVCMOS
interface levels.
NOTE:
1. Pullup and Pulldown refer to internal input resistors. See Capacitance table for typical values.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT8535-01 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER |
| IDT8535-01PG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LOW SKEW, 1-TO-4 LVCMOS-TO-3.3V LVPECL FANOUT BUFFER |
| IDT8535-01PGG | 功能描述:IC CLOCK BUFFER MUX 2:4 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:- 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| IDT8535-01PGG8 | 功能描述:IC CLOCK BUFFER MUX 2:4 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:- 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| IDT8535-01PGGI | 功能描述:IC CLOCK BUFFER MUX 2:4 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:- 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
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