參數(shù)資料
型號: IDT88P8342BHI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 17/98頁
文件大小: 0K
描述: IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝: 24
系列: *
其它名稱: 88P8342BHI
24
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
DATAPATH CONFIGURATION
A logical view of datapath configuration using Packet Fragment Processors
is shown in Figure 12, Logical View of Datapath Configuration Using PFPs.
Two PFPs are associated with each SPI-3 port, one for ingress and one for
egress.LogicalportsaremappedinternallyintoLogicalIdentifiers(“LIDs”,“LID
Map”)forthecontrolofeachper-LIDdataflowtoeachphysicalport,logicalport,
memory queue size, and backpressure threshold (watermark), by program-
ming the LID register files.
Figure 12. Logical view of datapath configuration using PFPs
LID - Logical Identifier
EN - LID enable flag
BRV - Bit reversal
LP - Logical port
PFP - Packet fragment processor
[LID] = LP | EN | BRV
SPI-3 Egress LID to LP Map
[LP] = LID | EN | BRV
SPI-3 Ingress LP to LID Map
[LID] = LP | EN
SPI-4 INGRESS DATA
SPI-4 EGRESS DATA
[LP] = LID | PPE | EN
LID
BRV
EN
LP
BRV
EN
LP
EN
256 LIDs
SPI-4 Egress LID to LP Map
PFP AND MEMORY
(ONE OF FOUR: ABCD)
PFP AND MEMORY
(ONE OF FOUR: ABCD)
PFP AND MEMORY
(ONE OF FOUR: ABCD)
PFP AND MEMORY
(ONE OF FOUR: ABCD)
PFP AND MEMORY
(ONE OF FOUR: ABCD)
PFP AND MEMORY
(ONE OF FOUR: ABCD)
SPI-3 INGRESS DATA
SPI-3 EGRESS DATA
PFP AND MEMORY
LID
EN
A/B
256 LPs
SPI-4 Ingress LP to LID Map
256 LPs
64 LIDs
6371 drwXB
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