參數(shù)資料
型號： IDT88P8342BHI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 89/98頁
文件大?。?/td> 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88P8342BHI
9
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
2. PIN DESCRIPTION
SPI-3 (two instantiations)
For the SPI-3 interfaces, each pin is used differently depending whether the
SPI-3isinLinkmodeorinPHYmode.EachoftheSPI-3interfacesisseparately
configurable for either Link or PHY mode. This configuration holds for both the
ingress and egress paths. The device pin is given a generic name, and
mapped to the standard pin name according to the mode of the interface (Link
or PHY).
TABLE 2 – SPI-3 INGRESS INTERFACE PIN DEFINITION
Generic Name
Specific Name
I/O type
Description
Mode
Link
PHY
I_FCLK
SPI3A_I_FCLK
I-ST
Ingress SPI-3 write clock
RFCLK
TFCLK
SPI3B_I_FCLK
LVTTL
RVAL
SPI3A_I_RVAL
B-PU
Receive data valid
RVAL (I)
RVAL (O)
SPI3B_I_RVAL
LVTTL
I_ENB
SPI3A_I_ENB
B-PU
Ingress read enable
RENB (O)
TENB (I)
SPI3B_I_ENB
LVTTL
I_DAT[31:0]
SPI3A_I_DAT[31:0]
I-PU
Ingress data bus
RDAT [31:0]
TDAT [31:0]
SPI3B_I_DAT[31:0]
LVTTL
I_MOD[1:0]
SPI3A_I_MOD[1:0]
I-PU
Ingress word modulus
RMOD [1:0]
TMOD [1:0]
SPI3B_I_MOD[1:0]
LVTTL
I_PRTY
SPI3A_I_PRTY
I-PU
Ingress parity
RPRTY
TPRTY
SPI3B_I_PRTY
LVTTL
I_SOP
SPI3A_I_SOP
I-PU
Ingress start of packet
RSOP
TSOP
SPI3B_I_SOP
LVTTL
I_EOP
SPI3A_I_EOP
I-PU
Ingress end of packet
REOP
TEOP
SPI3B_I_EOP
LVTTL
I_ERR
SPI3A_I_ERR
I-PU
Ingress EOP error
RERR
TERR
SPI3B_I_ERR
LVTTL
I_SX
SPI3A_I_SX
I-PU
Ingress start of transfer
RSX
TSX
SPI3B_I_SX
LVTTL
I/O type
Function
I_ST
Input with Schmitt trigger with weak pull up
I-PU
Input with weak pull up
B-PU
Bidirectional I/O with weak pull up
I_PD
Input with pull down
I
Input
O
Output
O-Z
Outputwithtri-state
OD
Output with open drain
TABLE 1 – I/O TYPES
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