參數(shù)資料
型號: IDT89HPES32T8ZHBXG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 34/37頁
文件大小: 0K
描述: IC PCI SW 32LANE 8PORT 500-SBGA
標準包裝: 27
系列: PRECISE™
類型: PCI Express 開關(guān) - Gen1
應(yīng)用: 服務(wù)器,儲存,通信,嵌入式,消費品
安裝類型: 表面貼裝
封裝/外殼: 500-LBGA
供應(yīng)商設(shè)備封裝: 500-SBGA(31x31)
包裝: 托盤
其它名稱: 89HPES32T8ZHBXG
6 of 37
March 25, 2008
IDT 89PES32T8 Data Sheet
PE7TP[3:0]
PE7TN[3:0]
O
PCI Express Port 7 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 7. When port 6 is merged with port 7, these signals
become port 6 transmit pairs for lanes 4 through 7.
PEREFCLKP[2:1]
PEREFCLKN[2:1]
I
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
REFCLKM
I
PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Signal
Type
Name/Description
MSMBADDR[4:1]
I
Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
MSMBCLK
I/O
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus. It is active and generating the clock only
when the EEPROM or I/O Expanders are being accessed.
MSMBDAT
I/O
Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
SSMBADDR[5,3:1]
I
Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
SSMBCLK
I/O
Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
SSMBDAT
I/O
Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Table 3 SMBus Interface Pins
Signal
Type
Name/Description
Table 2 PCI Express Interface Pins (Part 2 of 2)
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