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參數(shù)資料
| 型號： | IDT89HPES32T8ZHBXG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 36/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI SW 32LANE 8PORT 500-SBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | PRECISE™ |
| 類型： | PCI Express 開關(guān) - Gen1 |
| 應(yīng)用： | 服務(wù)器，儲存，通信，嵌入式，消費品 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 500-LBGA |
| 供應(yīng)商設(shè)備封裝： | 500-SBGA（31x31） |
| 包裝： | 托盤 |
| 其它名稱： | 89HPES32T8ZHBXG |
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March 25, 2008
IDT 89PES32T8 Data Sheet
GPIO[10]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P5RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 5
GPIO[11]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P6RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 6
GPIO[12]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P7RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 7
GPIO[13]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[14]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[15]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Signal
Type
Name/Description
CCLKDS
I
Common Clock Downstream. When the CCLKDS pin is asserted, it indi-
cates that a common clock is being used between the downstream device
and the downstream port.
CCLKUS
I
Common Clock Upstream. When the CCLKUS pin is asserted, it indi-
cates that a common clock is being used between the upstream device and
the upstream port.
MSMBSMODE
I
Master SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
P01MERGEN
I
Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low
internally via a 251K ohm resistor.
When this pin is low, port 0 is merged with port 1 to form a single x8 port.
The Serdes lanes associated with port 1 become lanes 4 through 7 of port
0. When this pin is high, port 0 and port 1 are not merged, and each oper-
ates as a single x4 port
P23MERGEN
I
Port 2 and 3 Merge. P23MERGEN is an active low signal. It is pulled low
internally via a 251K ohm resistor.
When this pin is low, port 2 is merged with port 3 to form a single x8 port.
The Serdes lanes associated with port 3 become lanes 4 through 7 of port
2. When this pin is high, port 2 and port 3 are not merged, and each oper-
ates as a single x4 port.
Table 5 System Pins (Part 1 of 2)
Signal
Type
Name/Description
Table 4 General Purpose I/O Pins (Part 2 of 2)
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| IDT89HPES34H16ZABL | 功能描述:IC PCI SW 34LANE 16PORT 1156FBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89HPES34H16ZABLG | 制造商:Integrated Device Technology Inc 功能描述:IC PCIE SW 34LANE 16PORT 1156BGA |
| IDT89HPES34H16ZABLGI | 制造商:Integrated Device Technology Inc 功能描述:IC PCIE SW 34LANE 16PORT 1156BGA |
| IDT89HPES34H16ZABLI | 功能描述:IC PCI SW 34LANE 16PORT 1156FBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT89HPES34H16ZABR | 功能描述:IC PCI SW 34LANE 16PORT 1156FBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:PRECISE™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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