– Ability to read and write any internal register via the SMBus
參數(shù)資料
型號: IDT89HPES8T5ZHBCG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 12/31頁
文件大?。?/td> 0K
描述: IC PCI SW 8LANE 5PORT 324-BGA
標(biāo)準(zhǔn)包裝: 84
系列: PRECISE™
類型: PCI Express 開關(guān) - Gen1
應(yīng)用: 服務(wù)器,儲存,通信,嵌入式,消費(fèi)品
安裝類型: 表面貼裝
封裝/外殼: 324-LBGA
供應(yīng)商設(shè)備封裝: 324-CABGA(19x19)
包裝: 托盤
其它名稱: 89HPES8T5ZHBCG
2 of 31
March 27, 2008
IDT 89HPES8T5 Data Sheet
Testability and Debug Features
– Ability to read and write any internal register via the SMBus
Eleven General Purpose Input/Output pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Packaged in 19mm x 19mm 324-ball BGA with 1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES8T5 provides the most efficient I/O connectivity solution for applications requiring high
throughput, low latency, and simple board layout with a minimum number of board layers. It provides connectivity for up to 5 ports across 8 integrated
serial lanes. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification revision 1.1.
The PES8T5 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transac-
tion layers. The PES8T5 can operate either as a store and forward switch or a cut-through switch and is designed to switch memory and I/O transac-
tions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to allow efficient switching for
applications requiring additional narrow port connectivity.
Figure 2 I/O Expansion Application
Memory
Processor
Memory
North
Bridge
PES8T5
Processor
x1
South
Bridge
GE
LOM
x4
GE
LOM
GE
1394
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