參數(shù)資料
型號(hào): IDT89HPES8T5ZHBCG
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 31/31頁(yè)
文件大?。?/td> 0K
描述: IC PCI SW 8LANE 5PORT 324-BGA
標(biāo)準(zhǔn)包裝: 84
系列: PRECISE™
類型: PCI Express 開(kāi)關(guān) - Gen1
應(yīng)用: 服務(wù)器,儲(chǔ)存,通信,嵌入式,消費(fèi)品
安裝類型: 表面貼裝
封裝/外殼: 324-LBGA
供應(yīng)商設(shè)備封裝: 324-CABGA(19x19)
包裝: 托盤(pán)
其它名稱: 89HPES8T5ZHBCG
9 of 31
March 27, 2008
IDT 89HPES8T5 Data Sheet
Pin Characteristics
Note: Some input pads of the PES8T5 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels.
This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
Function
Pin Name
Type
Buffer
I/O
Type
Internal
Resistor1
Notes
PCI Express Inter-
face
PE0RN[3:0]
I
CML
Serial Link
PE0RP[3:0]
I
PE0TN[3:0]
O
PE0TP[3:0]
O
PE2RN[0]
I
PE2RP[0]
I
PE2TN[0]
O
PE2TP[0]
O
PE3RN[0]
I
PE3RP[0]
I
PE3TN[0]
O
PE3TP[0]
O
PE4RN[0]
I
PE4RP[0]
I
PE4TN[0]
O
PE4TP[0]
O
PE5RN[0]
I
PE5RP[0]
I
PE5TN[0]
O
PE5TP[0]
O
PEREFCLKN[2:1]
I
LVPECL/
CML
Diff. Clock
Input
Refer toTable 9
PEREFCLKP[2:1]
I
REFCLKM
I
LVTTL
Input
pull-down
SMBus
MSMBADDR[4:1]
I
LVTTL
Input
pull-up
MSMBCLK
I/O
STI2
pull-up on board
MSMBDAT
I/O
STI
pull-up on board
SSMBADDR[5,3:1]
I
Input
pull-up
SSMBCLK
I/O
STI
pull-up on board
SSMBDAT
I/O
STI
pull-up on board
General Purpose I/O
GPIO[10:0]
I/O
LVTTL
High Drive
pull-up
Table 8 Pin Characteristics (Part 1 of 2)
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