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參數(shù)資料
| 型號： | IDTCSPU877NL8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | CSPU877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40 |
| 封裝： | PLASTIC, VFQFPN-40 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 140K |
| 代理商： | IDTCSPU877NL8 |
6
COMMERCIALTEMPERATURERANGE
IDTCSPU877
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
TIMING REQUIREMENTS
Symbol
Parameter
Min.
Max.
Unit
fCLK
OperatingClockFrequency(1,2,3)
125
340
MHz
ApplicationClockFrequency(2,4)
160
340
MHz
tDC
Input Clock Duty Cycle
40
60
%
tL
StabilizationTime(5)
15
μs
NOTES:
1. 270MHz max clock frequency for parts assembled and tested prior to WW37.
2. The PLL will track a spread spectrum clock input.
3. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications. To be used only for low speed system debug.
4. Application clock frequency is the range over which timing specifications apply.
5. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the
stabilization time is also the time required for the PLL circuit to obtain phase lock of its feedback signal to its reference signal when CLK and CLK go to a logic LOW state, enters
the power-down mode, and later return to active operation. CLK and CLK may be left floating after they have been driven LOW for one complete clock cycle.
AC ELECTRICAL CHARACTERISTICS(1)
Symbol
Description
Test Conditions
Min.
Typ.(2)
Max.
Unit
tPLH(2)
LOW to HIGH Level Propagation Delay Time
AVDD = GND, OE = H, OS = L,
TBD
ns
CLK to any output
tPHL(2)
HIGH to LOW Level Propagation Delay Time
AVDD = GND, OE = H, OS = L,
TBD
ns
CLK to any output
tJIT(CC+)
Jitter(cycle-to-cycle)
166/200/266MHz
0
40
ps
tJIT(CC-)
0
-40
tJIT(PER)(3)
Jitter(period)
166/200/266MHz
-40
40
ps
tJIT(HPER)(3)
Half-PeriodJitter
166/200/266MHz
-60
60
ps
tSLR(O)(1,4)
OutputClockSlewRate(single-ended)
166/200/266MHz (20% to 80%)
1.5
2.5
3
V/ns
tSLR(I)(1,4)
OutputEnable(OE)
0.5
V/ns
Input Clock Slew Rate
1
2.5
4
t()(5)
StaticPhaseOffset
166/200/266MHz
-50
50
ps
t()DYN
DynamicPhaseOffset
TBD
tSK(O)
Output Skew
40
ps
tEN
Output Enable to any Y or Y
8ns
tDIS
Output Disable to any Y or Y
8ns
VOX(6)
ACDifferentialOutputCrosspointVoltage
Differentialoutputsterminatedwith120
Ω
(VDDQ/2)-0.1
(VDDQ/2)+0.1
V
VID(AC)
ACDifferentialInputVoltage
0.6
VDDQ+0.4
V
VIX
ACDifferentialInputCrosspointVoltage
(VDDQ/2)-0.15
(VDDQ/2)+0.15
V
The PLL on the CSPU877 will meet all the above test parameters while supporting SSC synthesizers with the following parameters:
SSC
ModulationFrequency
30
33
KHz
SSC
ClockInputFrequencyDeviation
0
-0.5
%
f3dB
PLLLoopBandwidth
2
MHz
NOTES:
1. There are two different terminations that are used with the above AC tests. The output load shown in figure 1 is used to measure the input and output differential pair cross-voltage
only. The output load shown in figure 2 is used to measure all other tests, including input and output slew rates. For consistency, use 50
Ω equal length cables with SMA connectors
on the test board.
2. Refers to transition of non-inverting output.
3. Period jitter and half-period jitter specifications are seperate specifications that must be met independently of each other.
4. To eliminate the impact of input slew rates on static phase offset, the input slew rates of reference clock input (CLK, CLK) and feedback clock input (FBIN, FBIN) are recommended
to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these nominal values is not mandatory if it can be adequately demonstrated
that alternative characteristics meet the requirements of the registered DDR2 DIMM application.
5. Static phase offset does not include jitter.
6. VOX is specified at the DDR DRAM clock input or test load.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTCSPUA877A | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPUA877ABVG | 功能描述:IC SDRAM CLK DVR 1:10 52-VFBGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| IDTCSPUA877ABVG8 | 功能描述:IC PLL CLK DVR SDRAM 52-CABGA RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| IDTCSPUA877ANLG | 功能描述:IC PLL CLK DVR SDRAM 40-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| IDTCSPUA877ANLG8 | 功能描述:IC PLL CLK DVR SDRAM 40-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
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