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參數(shù)資料
| 型號： | IDTCV107EPVG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 11/21頁 |
| 文件大?。?/td> | 108K |
| 代理商： | IDTCV107EPVG8 |
COMMERCIALTEMPERATURERANGE
IDTCV107E
CLOCKGENERATORFORDESKTOPPCPLATFORMS
19
PD#, POWER DOWN
PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power. When PD# is asserted low all clocks will be driven low
before turning off the VCO. In PD# de-assertion all clocks will start without glitches.
PD# ASSERTION
PD# should be sampled low by two consecutive CPU# rising edges before stopping clocks. All single-ended clocks will be held low on their next high to
low transition. All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register determining to drive
mode is set to ‘tri-state’, the differential pair will be stopped in tri-state mode, undriven. When the drive mode but corresponding to the CPU or SRC clock of
interest is set to ‘0’ the true clock will be driven high at 2 x IREF and the complementary clock will be tristated. If the control register is programmed to ‘1’ both
clocks will be tristated.
PWRDWN#
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
PWRDWN#
CPU
CPU#
SRC
SRC#
PCIF/PCI
USB
3V66
REF
1
Normal
33MHz
48MHz
66MHz
14.318MHz
0IREF * 2 or float
Float
IREF * 2 or float
Float
Low
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