- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67716 > IDTCV107EPVG8 (INTEGRATED DEVICE TECHNOLOGY INC) 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 PDF資料下載
參數(shù)資料
| 型號： | IDTCV107EPVG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 3/21頁 |
| 文件大?。?/td> | 108K |
| 代理商： | IDTCV107EPVG8 |
COMMERCIALTEMPERATURERANGE
IDTCV107E
CLOCKGENERATORFORDESKTOPPCPLATFORMS
11
BYTE 26: CPU PLL CONTROL
Bit
Output(s) Affected
Description/Function
0
1
Type
Power On
7
WDBS2
At the event of WD hard alarm time out,
RW
1
6
WDBS1
If Byte 32 bit 7 = 1, CPU frequency is
RW
0
5
WDBS0
selected by WDBS[2:0] WDCFS[2:0](1)
RW
0
4
CSMC2
CPU SMC2, SMC table
RW
0
3
CSMC1
CPU SMC1, SMC table
RW
1
2
CSMC0
CPU SMC0, SMC table
RW
0
1
CPN9
CPU PLL N9
RW
0
CPN8
CPU PLL N8
RW
1
NOTE:
1. See SW FREQUENCY SELECTION table.
BYTE 27: CPU PLL N PROGRAMMING
In CPU N programming mode, CPU frequency = CPN[9:0] * band resolution. CPN0 has to be written for the CPN[9:0] to be loaded into PLL N driver. See
SW FREQUENCY SELECTION table.
Bit
Output(s) Affected
Description/Function
0
1
Type
Power On
7
CPN7
CPU PLL N7
RW
0
6
CPN6
CPU PLL N6
RW
0
5
CPN5
CPU PLL N5
RW
1
4
CPN4
CPU PLL N4
RW
0
3
CPN3
CPU PLL N3
RW
1
2
CPN2
CPU PLL N2
RW
0
1
CPN1
CPU PLL N1
RW
1
0
CPN0
CPU PLL N0
RW
0
BYTE 28: AGP/PCI PLL CONTROL
Bit
Output(s) Affected
Description/Function
0
1
Type
Power On
7
AFS2
See AGP/PCI FREQUENCY SELECTION table
RW
0
6
AFS1
See AGP/PCI FREQUENCY SELECTION table
RW
0
5
AFS0
See AGP/PCI FREQUENCY SELECTION table
RW
0
4
WDAFS2
AGP/PCI WD hard alarm time out frequency selection
RW
0
3
WDAFS1
AGP/PCI WD hard alarm time out frequency selection
RW
0
2
WDAFSO
AGP/PCI WD hard alarm time out frequency selection
RW
0
1
APN9
AGP/PCI PLL N9
RW
0
APN8
AGP/PCI PLL N8
RW
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDTCV110NPVG8 | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| IDTCV115-2PVG8 | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| IDTCV126PAG | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| IDTCV126PVG8 | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| IDTCV128PAG8 | CV128 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO56 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDTCV109E | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:CLOCK GENERATOR FOR DESKTOP PC PLATFORMS |
| IDTCV109EPV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:CLOCK GENERATOR FOR DESKTOP PC PLATFORMS |
| IDTCV110JP | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| IDTCV110JPV | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
| IDTCV110JPVG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。