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參數(shù)資料
| 型號： | IDTCV107EPVG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大小： | 108K |
| 代理商： | IDTCV107EPVG8 |
COMMERCIALTEMPERATURERANGE
IDTCV107E
CLOCKGENERATORFORDESKTOPPCPLATFORMS
15
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VIH
3.3V Input HIGH Voltage
3.3V ± 5%
2
—
VDD + 0.3
V
VIL
3.3V Input LOW Voltage
3.3V ± 5%
VSS - 0.3
—
0.8
V
IIH
Input HIGH Current
VIN = VDD
–5
—
5
A
IIL1
Input LOW Current
VIN = 0V, inputs with no pull-up resistors
–5
—
A
IIL2
Input LOW Current
VIN = 0V, inputs with pull-up resistors –200
—
A
IDD3.3OP
Operating Supply Current
Full active, CL = full load
—
400
mA
IDD3.3PD
Powerdown Current
All differential pairs driven
—
70
mA
All differential pairs tri-stated
—
12
FI
Input Frequency(2)
VDD = 3.3V
—
14.31818
—
MHz
LPIN
Pin Inductance(3)
——
7
nH
CIN
Logic inputs
—
5
COUT
Input Capacitance(3)
Output pin capacitance
—
6
pF
CINX
X1 and X2 pins
—
5
TSTAB
Clock Stabilization(3,4)
From VDD power-up or de-assertion of PD# to first clock
—
1.8
ms
Modulation Frequency(3)
Triangular modulation
30
—
33
KHz
TDRIVE_SRC(3)
SRC output enable after PCI_Stop# de-assertion
—
15
ns
TDRIVE_PD#(3)
CPU output enable after PD# de-assertion
—
300
us
TFALL_PD#(3)
Fall time of PD#
—
5
ns
TRISE_PD#(4)
Rise time of PD#
—
5
ns
TDRIVE_CPU_Stop#(3)
CPU output enable after CPU_Stop# de-assertion
—
10
us
TFALL_CPU_Stop#(3)
Fall time of PD#
—
5
ns
TRISE_CPU_Stop#(4)
Rise time of PD#
—
5
ns
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%
NOTES:
1.
Available to CV104, CV105, CV107, and CV109.
2.
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
3.
This parameter is guaranteed by design, but not 100% production tested.
4.
See TIMING DIAGRAMS for timing requirements.
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