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| 型號(hào)： | IDTIDT71P71604200BQ |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 18Mb Pipelined DDR⑩II SRAM Burst of 2 |
| 中文描述： | 35.7流水線的DDR II SRAM的突發(fā)⑩2 |
| 文件頁數(shù)： | 15/23頁 |
| 文件大?。?/td> | 241K |
| 代理商： | IDTIDT71P71604200BQ |
6.42
15
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-J TAG
This part contains an IEEE standard 1149.1 Compatible Test Access
Port (TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during
manufacturing and systemdiagnostics. In conformance wth IEEE 1149.1,
the SRAMcontains a TAP controller, Instruction register Bypass Regis-
ter and ID register The TAP controller has a standard 16-state machine
that resets internally upon power-up; therefore, the TRST signal is not
J TAG Block Diagram
J TAG Instruc tion Coding
IR2
IR1
IR0
Instruction
TDO Output
Notes
0
0
0
EXTEST
Boundary Scan Register
0
0
1
IDCODE
Identification register
2
0
1
0
SAMPLE-Z
Boundary Scan Register
1
0
1
1
RESERVED
Do Not Use
5
1
0
0
SAMPLE/PRELOAD Boundary Scan register
4
1
0
1
RESERVED
Do Not Use
5
1
1
0
RESERVED
Do Not Use
5
1
1
1
BYPASS
Bypass Register
3
6112 tbl 13
TAP Controller S tate Diagram
SRAM
CORE
BYPASS Reg.
Identification Reg.
Instruction Reg
.
Control Signal
s
TAP Controller
TDI
TMS
TCK
TDO
6112 drw 18
Test Logic Reset
Run Test Idle
Select DR
Capture DR
Pause DR
Exit 2 DR
Update DR
Shift DR
Exit 1 DR
Select IR
Capture IR
Pause IR
Exit 2 IR
Update IR
Shift IR
Exit 1 IR
0
0
0
0
0
0
1
1
1
1
1
1
1
0
6112 drw 17
0
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
NOTE:
1. Places DQs in Hi-Z in order to sample all input data regardless of other SRAM
inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of
the external TDI data.
3. Bypass register is initialized to Vss when BYPASS instruction is invoked.
The Bypass Register also holds serially loaded TDI when exiting the Shift DR
states.
4. SAMPLE instruction does not place output pins in Hi-Z.
5. This instruction is reserved for future use.
required. It is possible to use this device without utilizing the TAP. To
disable the TAP controller without interfacing with normal operation of the
SRAM TCK must be tied to VSS to preclude a md level input. TMS and
TDI are designed so an undriven input will produce a response identical
to the application of a logic 1, and may be left unconnected, but they may
also be tied to VDD through a resistor TDO should be left unconnected.
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|---|---|
| IDTIDT71P71604250BQ | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SRAM Burst of 2 |
| IDTIDT71P71804167BQ | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SRAM Burst of 2 |
| IDTIDT71P71804200BQ | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SRAM Burst of 2 |
| IDTIDT71P71804250BQ | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SRAM Burst of 2 |
| IDTIDT71P79104167BQ | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:18Mb Pipelined DDR⑩II SIO SRAM Burst of 2 |
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