參數資料
型號： IDTIDT71P79804250BQ
廠商： Integrated Device Technology, Inc.
英文描述： 18Mb Pipelined DDR⑩II SIO SRAM Burst of 2
中文描述： 35.7流水線⑩二二氧化硅的DDR SRAM的爆裂2
文件頁數： 14/23頁
文件大?。?/td> 641K
代理商： IDTIDT71P79804250BQ
6.42
14
IDT71P79204 (2Mx8-Bit), 71P79104 (2Mx9-Bit), 71P79804 (1Mx18-Bit) 71P79604 (512Kx36-Bit)
18 Mb DDR II SIO SRAM Burst of 2 Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(V
DD
= 1.8 ± 100mV, V
DDQ
= 1.4V to 1.9V, Commercial and Industrial Temperature Ranges)
(3,7)
Symbol
Parameter
267MHz
250MHz
200MHz
167MHz
Unit
Notes
Mn.
Max
Mn.
Max
Min.
Max
Mn.
Max
Clock Parameters
t
KHKH
Clock Cycle Time (K
,
K
,C,
C
)
3.75
6.30
4.00
6.30
5.00
7.88
6.00
8.40
ns
t
KC var
Clock Phase Jitter (K,
K
,C,
C
)
-
-
-
0.20
-
0.20
-
0.20
ns
1,5
t
KHKL
Clock High Time (K,
K
,C,
C
)
1.50
-
1.60
-
2.00
-
2.40
-
ns
8
t
KLKH
Clock LOW Time (K,
K
,C,
C
)
1.50
-
1.60
-
2.00
-
2.40
-
ns
8
t
KH
K
H
Clock to
clock
(K
→
K
,C
→
C
)
1.69
-
1.80
-
2.20
-
2.70
-
ns
9
t
K
HKH
Clock
to clock (
K
→
K,
C
→
C)
1.69
-
1.80
-
2.20
-
2.70
-
ns
9
t
KHCH
Clock to data clock (K
→
C,
K
→
C
)
0.00
1.69
0.00
1.80
0.00
2.30
0.00
2.80
ns
t
KC lock
DLL lock time (K, C)
1024
-
1024
-
1024
-
1024
-
cycles
2
t
KC reset
K static to DLL reset
30
-
30
-
30
-
30
-
ns
Output Parameters
t
CHQV
C,
C
HIGH to output valid
-
0.45
-
0.45
-
0.45
-
0.50
ns
3
t
CHQX
C,
C
HIGH to output hold
-0.45
-
-0.45
-
-0.45
-
-0.50
-
ns
3
t
CHCQV
C,
C
HIGH to echo clock valid
-
0.45
-
0.45
-
0.45
-
0.50
ns
3
t
CHCQX
C,
C
HIGH to echo clock hold
-0.45
-
-0.45
-
-0.45
-
-0.50
-
ns
3
t
CQHQV
CQ,
CQ
HIGH to output valid
-
0.30
-
0.30
-
0.35
-
0.40
ns
t
CQHQX
CQ,
CQ
HIGH to output hold
-0.30
-
-0.30
-
-0.35
-
-0.40
-
ns
t
CHQZ
C HIGH to output High-Z
-
0.45
-
0.45
-
0.45
-
0.50
ns
3,4,5
t
CHQX1
C HIGH to output Low-Z
-0.45
-
-0.45
-
-0.45
-
-0.50
-
ns
3,4,5
Set-Up Times
t
AVKH
Address valid to K,
K
rising edge
0.50
-
0.50
-
0.60
-
0.70
-
ns
6
t
IVKH
R/
W
inputs valid to K,
K
rising edge
0.50
-
0.50
-
0.60
-
0.70
-
ns
t
DVKH
Data-in and
BWx
/
NWx
valid to K,
K
rising edge
0.35
-
0.35
-
0.40
-
0.50
-
ns
Hold Times
t
KHAX
K,
K
rising edge to address hold
0.50
-
0.50
-
0.60
-
0.70
-
ns
6
t
KHIX
K,
K
rising edge to R/
W
inputs hold
0.50
-
0.50
-
0.60
-
0.70
-
ns
t
KHDX
K,
K
rising edge to data-in and
BWx
/
NWx
hold
0.35
-
0.35
-
0.40
-
0.50
-
ns
6432 tbl 11
NOTES:
1. Clock phase jitter is the variance fromclock rising edge to the next expected clock rising edge.
2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
3. If C,
C
are tied High, K,
K
become the references for C,
C
timng parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention
because tCHQX1 is a MIN parameter that is worse case at totally different test conditions (0°C, 1.9V) than tCHQZ, which is a MAX parameter
(worst case at 70°C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. During production testing, the case temperature equals TA.
8. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).
9. Clock to
clock
time (tKH
K
H) and
Clock
to clock time (t
K
HKH) should be within 45% to 55% of the cycle time (tKHKH).
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