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參數(shù)資料
| 型號： | IDTQS5LV919-133J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5LV SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 111K |
| 代理商： | IDTQS5LV919-133J |
7
INDUSTRIALTEMPERATURERANGE
QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PLL OPERATION
The Phase Locked Loop (PLL) circuit included in the QS5LV919 provides
for replication of incoming SYNC clock signals. Any manipulation of that
signal, such as frequency multiplying or inversion is performed by digital
logic following the PLL (see the block diagram). The key advantage of the
SIMPLIFIED DIAGRAM OF QS5LV919 FEEDBACK
The phase difference between the output and the input frequencies feeds
the VCO which drives the outputs. Whichever output is fed back, it will
stabilize at the same frequency as the input. Hence, this is a true negative
feedback closed loop system. In most applications, the output will optimally
have zero phase shift with respect to the input. In fact, the internal loop filter
on the QS5LV919 typically provides within 150ps of phase shift between
input and output.
PLL circuit is to provide an effective zero propagation delay between the
output and input signals. In fact, adding delay circuits in the feedback path,
‘propagation delay’ can even be negative! A simplified schematic of the
QS5LV919 PLL circuit is shown below.
If the user wishes to vary the phase difference (typically to compensate
for backplane delays), this is most easily accomplished by adding delay
circuits to the feedback path. The respective output used for feedback will
be advanced by the amount of delay in the feedback path. All other outputs
will retain their proper relationships to that output.
Q
Q/2
Q
VCO
/2
PHASE
DETECTO R
INPU T
2xQ
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