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參數(shù)資料
| 型號： | IDTQS5LV919-133J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 5LV SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 111K |
| 代理商： | IDTQS5LV919-133J |
5
INDUSTRIALTEMPERATURERANGE
QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
NOTES:
1.
See Test Loads and Waveforms for test load and termination.
2.
Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade).
3.
Measured in open loop mode PLL_EN = 0.
4.
Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies.
5.
Skew measured at selected synchronization edge.
6.
tPD measured at device inputs at 0.5VDD, Q output at 80MHz.
INPUT TIMING REQUIREMENTS
Symbol
Description(1)
Min.
Max.
Unit
tR, tF
Maximum input rise and fall times, 0.8V to 2V
—
3
ns
FI
Input Clock Frequency, SYNC0, SYNC1(1)
2.5
100
MHz
tPWC
Input clock pulse, HIGH or LOW(2)
2—
ns
DH
Input duty cycle, SYNC0, SYNC1(2)
25
75
%
NOTES:
1.
See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and
FREQ_SEL combinations.
2.
Where pulse witdh implied by DH is less than tWPC limit, tWPC limit applies
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter(1)
Min.
Max.
Unit
tSKR
Output Skew Between Rising Edges, Q0-Q4 (and Q/2 if
PE = LOW)(2)
—
300
ps
tSKF
Output Skew Between Falling Edges, Q0-Q4 (and Q/2 if
PE = HIGH)(2)
—
300
ps
tSKALL
Output Skew, All Outputs(2, 5)
—
500
ps
tPW
Pulse Width, 2xQ output, >40MHz
TCY/2
0.4
TCY/2 + 0.4
ns
tPW
Pulse Width, Q0-Q4, Q5, Q/2 outputs, 80MHz
TCY/2
0.4
TCY/2 + 0.4
ns
tJ
Cycle-to-Cycle Jitter(4)
0.15
0.15
ns
tPD
SYNC Input to Feedback Delay(6)
500
0
ps
tLOCK
SYNC to Phase Lock
—
10
ms
tPZH
Output Enable Time, OE/
RST LOW to HIGH(3)
014
ns
tPZL
tPHZ
Output Disable Time, OE/
RST HIGH to LOW(3)
014
ns
tPLZ
tR,tF
Output Rise/Fall Times, 0.8V
2V
0.3
2
ns
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