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參數(shù)資料
| 型號： | IDTQS5LV919-133J |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5LV SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 111K |
| 代理商： | IDTQS5LV919-133J |
3
INDUSTRIALTEMPERATURERANGE
QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PIN DESCRIPTION
Pin Name
I/O
Description
SYNC0
I
Referenceclockinput
SYNC1
I
Referenceclockinput
REF_SEL
I
Reference clock select. When 1, selects SYNC1. When 0, selects SYNC0.
FREQ_SEL
I
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency.
FEEDBACK
I
PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different
output frequency relationships. See the Frequency Selection Table for more information.
Q0 -Q4
O
Clock outputs
Q5
O
Clock output. Matched in frequency, but inverted with respect to Q.
2xQ
O
Clock output. Matched in phase, but frequency is double the Q frequency.
Q/2
O
Clock output. Matched in phase, but frequency is half the Q frequency.
LOCK
O
PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be
synchronized to the inputs.
OE/
RST
I
Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When
1, outputs are enabled.
PLL_EN
I
PLL enable. Enables and disables the PLL. Useful for testing purposes.
PE
I
When
PE is LOW, outputs are synchronized with the positive edge of SYNC. When HIGH, outputs are synchronized with
the negative edge of SYNC.
VDD
—
Power supply for output buffers.
AVDD
—
Power supply for phase lock loop and other internal circuitries.
GND
—
Ground supply for output buffers.
AGND
—
Ground supply for phase lock loop and other internal circuitries.
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: TA = –40°C to +85°C, AVDD / VDD = 3.3V ± 0.3V
Symbol
Description
– 55
– 70
– 100
– 133
– 160
Units
FMAX_2XQ
Max Frequency, 2xQ
55
70
100
133
160
MHz
FMAX_Q
Max Frequency, Q0 - Q4, Q5
27.5
35
50
66.5
80
MHz
FMAX_Q/2
Max Frequency, Q/2
13.75
17.5
25
33.25
40
MHz
FMIN_2XQ
Min Frequency, 2xQ
20
MHz
FMIN_Q
Min Frequency, Q0 - Q4, Q5
10
MHz
FMIN_Q/2
Min Frequency, Q/2
5
MHz
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