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| 型號(hào)： | IMST425-J25S |
| 元件分類： | 32位微控制器 |
| 英文描述： | 32-Bit Microprocessor |
| 中文描述： | 32位微處理器 |
| 文件頁(yè)數(shù)： | 14/74頁(yè) |
| 文件大?。?/td> | 563K |
| 代理商： | IMST425-J25S |
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IMS T400
/ 74
14
5
External memory interface
The External Memory Interface (EMI) allows access to a 32 bit address space, supporting dynamic and
static RAMaswellas ROM andEPROM.EMI timing canbeconfiguredat
Reset
to caterfor most memory
types andspeeds,andaprogramissuppliedwiththeTransputerDevelopmentSystemtoaidinthisconfig-
uration.
There are 17 internal configurations which can be selected by a single pin connection (page 31). If none
are suitable the user can configure the interface to specific requirements, as shown in page 33.
The external memory cycle is divided into six
Tstates
with the following functions:
T1
Address setup time before address valid strobe.
T2
Address hold time after address valid strobe.
T3
Read cycle tristate or write cycle data setup.
T4
Extendable data setup time.
T5
Read or write data.
T6
Data hold.
Under normal conditions each
Tstate
may be from one to four periods
Tm
long, the duration being set
during memoryconfiguration.Thedefaultconditionon
Reset
isthatall
Tstates
arethemaximumfourperi-
ods
Tm
long to allow external initialisation cycles to read slow ROM.
Period
T4
can be extended indefinitely by adding externally generated wait states.
An external memory cycle is always an even number of periods
Tm
in length and the start of
T1
always
coincideswith arising edgeof
ProcClockOut
.If thetotalconfiguredquantityofperiods
Tm
isan oddnum-
ber,one extra period
Tm
will be added at the end of
T6
to force the start of the next
T1
to coincide with
a rising edge of
ProcClockOut
. This period is designated
E
in configuration diagrams (figure 5.19).
During aninternalmemory access cycletheexternalmemory interfacebus
MemAD2-31
reflectstheword
address used toaccess internal RAM,
MemnotWrD0
reflects theread/write operationand
MemnotRfD1
is high; all control strobes are inactive. This is true unless and until a memory refresh cycle or DMA
(memory request) activity takes place, when the bus will carry the appropriate external address or data.
The bus activity is not adequate to trace the internal operation of the transputer in full, but may be used
for hardware debugging in conjunction with peek and poke (page 8).
ProcClockOut
MemAD2–31
MemnotRfD1
MemnotWrD0
Address
Address
Address
Write
Read
Read
Figure 5.1
IMS T400 bus activity for internal memory cycle
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