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| 型號(hào)： | IMST425-J25S |
| 元件分類： | 32位微控制器 |
| 英文描述： | 32-Bit Microprocessor |
| 中文描述： | 32位微處理器 |
| 文件頁(yè)數(shù)： | 33/74頁(yè) |
| 文件大?。?/td> | 563K |
| 代理商： | IMST425-J25S |
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5 External memory interface
/ 74
33
MemnotWrD0
MemnotRfD1
MemAD2
MemAD3
MemAD31
MemConfig
MemConfig
64
periods
of
ClockIn
Periods of ClockIn
16
periods
of
ClockIn
Read at
7FFFFF6C
Read at
7FFFFF70
Delay
Internal configuration
External configuration
0 00 0 11
2 46 8 02
6 6 6
0 2 4
5
8
1
2
Internal configuration:
MemConfig
connected to
MemAD2
External configuration:
MemConfig
connected to inverse of
MemAD3
1
2
Figure 5.18
IMS T400 internal configuration scan
5.7.2
External configuration
If
MemConfig
isheldlowuntil
MemnotWrD0
goeslowtheinternalconfigurationisignoredand anexternal
configuration will be loaded instead. An external configuration scan always follows an internal one, but if
an internal configuration occurs any external configuration is ignored.
Theexternal configurationscancomprises36 successiveexternalreadcycles,using thedefaultEMI con-
figuration preset by
MemAD31
. However,instead ofdata beingreadon thedatabus asfor a normalread
cycle, onlya singlebit ofdatais readon
MemConfig
at eachcycle. Addressesputout onthebus foreach
read cycle are shown intable 5.10,and aredesigned to address ROM atthe topof the memory map. The
table shows the data to be held in ROM; data required at the
MemConfig
pin is the inverse of this.
MemConfig
is typically connected via an inverter to
MemnotWrD0
. Data bit zero of the least significant
byte of each ROM word then provides the configuration data stream. By switching
MemConfig
between
variousdatabuslines upto32 configurationscanbestoredinROM,one perbitof thedatabus.
MemCon-
fig
can be permanently connected to a data line or to
GND
. Connecting
MemConfig
to
GND
gives all
Tstates
configured to four periods;
notMemS1
pulse of maximum duration;
notMemS2-4
delayed by
maximum; refresh interval 72 periods of
ClockIn
; refresh enabled; late write.
The external memory configuration table 5.10 shows the contribution of each memory address to the
13 configurationfields. Thelowest12 words(#7FFFFF6C to#7FFFFF98, fields1 to 6)definethe number
of extra periods
Tm
to be added to each
Tstate
. If field 2 is 3 then three extra periods will be added to
T2
to extend it to the maximum of four periods.
The nextfive addresses (field 7) definetheduration of
notMemS1
and thefollowing fifteen (fields8 to 10)
definethe delaysbefore strobes
notMemS2-4
become active. Thefive bits allocatedto each strobeallow
durations of from 0 to 31 periods
Tm
, as described in strobes page 15.
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