參數(shù)資料
型號： IMST425J20S
英文描述： Peripheral IC
中文描述： 外圍芯片
文件頁數(shù)： 41/74頁
文件大?。?/td> 563K
代理商： IMST425J20S
7 Links
/ 74
41
7
Links
Twoidentical INMOSbi-directional serial linksprovide synchronizedcommunicationbetween processors
and with the outsideworld. Each linkcomprises an input channel and output channel. Alink betweentwo
transputers isimplemented byconnecting alinkinterface onone transputerto a linkinterfaceon theother
transputer. Everybyteof datasentonalinkisacknowledgedontheinputofthesamelink,thuseachsignal
line carries both data and control information.
The quiescent state of a link output is low. Each data byte is transmitted as a high start bit followed by a
one bit followed by eight data bits followed by a low stopbit. The leastsignificant bitof data is transmitted
first. After transmittinga data byte the sender waits for the acknowledge,which consists of a high startbit
followed by a zero bit. The acknowledge signifies both that a process was able to receive the acknowl-
edged data byte and that the receiving link is ableto receive another byte. The sending link reschedules
the sending process only after the acknowledge for the final byte of the message has been received.
TheIMST400linksallowanacknowledgepackettobesentbeforethedatapackethasbeenfullyreceived.
This overlapped acknowledge technique is fully compatible with all other INMOS transputer links.
TheIMS T400 linkssupport thestandard INMOS communication speedof 10 Mbits/sec.In addition they
can be used at 5 or 20 Mbits/sec. Links are not synchronised with
ClockIn
or
ProcClockOut
and are in-
sensitive to their phases. Thus links from independently clocked systems may communicate, providing
only that the clocks are nominally identical and within specification.
Links are TTL compatible and intendedto be usedin electrically quiet environments, between devices on
a singleprinted circuitboard orbetween two boardsviaa backplane. Direct connectionmay be madebe-
tween devices separated by a distance of less than 300 millimetres. For longer distances a matched
100 ohm transmission line should be used with series matching resistors
RM
. Whenthis is done the line
delay should be less than 0.4 bit time to ensure that the reflection returns before thenext data bit is sent.
Buffers may be used for very long transmissions. If so, their overall propagation delay should be stable
within the skew tolerance of the link, although the absolute value of the delay is immaterial.
Linkspeedscan beset by
LinkSpecial
,
Link0Special
and
Link1Special
.Table7.1 shows uni-directional
and bi-directional data rates inKbytes/sec for each link speed;
LinknSpecial
is to be read as
Link0Spe-
cial
when selecting link 0 speed and as
Link1Special
for link 1. Data rates are quoted for a transputer
using internal memory,and will be affectedby a factor depending on the number of external memory ac-
cesses and the length of the external memory cycle.
Link
Special
Linkn
Special
Kbytes/sec
Uni
910
450
910
1740
Mbits/sec
Bi
0
0
1
1
0
1
0
1
10
5
10
20
1250
670
1250
2350
Table7.1
Speed Settings for Transputer Links
0
1
2
3
4
5
6
7
Data
Ack
H
H
L
L
H
Figure 7.1
IMS T400 link data and acknowledge packets
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相關代理商/技術參數(shù)
參數(shù)描述
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IMST425-J25S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor
IMST425-X25S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor
IMST800C-G17S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC
IMST800C-G20S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC
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