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| 型號(hào)： | INSTRUCTIN603EWP |
| 英文描述： | Optimizing the Instruction Execution on the 603e |
| 中文描述： | 優(yōu)化了603e的指令執(zhí)行 |
| 文件頁數(shù)： | 27/54頁 |
| 文件大?。?/td> | 325K |
| 代理商： | INSTRUCTIN603EWP |
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RISC Microprocessor Division
Page 27
Integer Unit
Most integer instructions only take one cycle to execute; thus the integer unit does not usually stall.
The only times that the integer unit stalls is if it is executing multiple-clock integer instructions such as
trap, multiply, and divide, or if the instruction cannot execute because it is dependent on the results of
another operation. The internal bus structure of the 603e allows an integer instruction to immediately
access any operand as soon as it becomes valid.
System Register Unit
The SRU handles all of the special purpose register instructions, context synchronizing instructions,
and certain integer add/compare operations. Some special purpose register instructions are also
inherently context synchronizing. Context synchronization will always cause some instruction stall, but
this is almost always critical to guarantee correct operation. Integer operations in the SRU take only
one cycle to execute, thereby causing no stalls.
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