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| 型號： | INSTRUCTIN603EWP |
| 英文描述： | Optimizing the Instruction Execution on the 603e |
| 中文描述： | 優(yōu)化了603e的指令執(zhí)行 |
| 文件頁數(shù)： | 9/54頁 |
| 文件大?。?/td> | 325K |
| 代理商： | INSTRUCTIN603EWP |
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RISC Microprocessor Division
Page 9
Execution units
The Integer Unit accepts all integer instructions.
The System Register Unit accepts all synchronizing, condition register, and system register
instructions. Since these instructions appear infrequently, the SRU also accepts basic add and
compare instructions.
The Floating-Point Unit accepts all instructions utilizing the FP registers (other than loads and
stores).
The Branch Processing Unit redirects instruction fetches, performs prediction and helps control
speculative execution, and folds appropriate branches out of the pipeline to permit an effective branch
cycle time of zero.
The Load/Store Unit accepts instructions accessing data cache and memory.
Registers
The 603e supports 32 general-purpose registers (GPRs) that are 32 bits wide, and 32 floating-point
registers (FPRs) that are 64 bits wide. These two register files are supported by rename registers
which allow quick forwarding of data, in order to reduce stalls based on data dependencies. There are
five GPR rename registers and four FPR rename registers.
As an example of usage, suppose we have an integer divide instruction which is computing the value of
a given GPR, followed by a store instruction which must store this value to memory. When the divide is
dispatched to the IU, the GPR is assigned a GPR rename register. The store is then dispatched to the
LSU and must wait for the value to become valid. When the value is computed, the store immediately
gets the value through the GPR rename bus, and can begin storing the value at the same time it is
being written back to the GPR file.
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