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參數資料
| 型號： | INSTRUCTIN603EWP |
| 英文描述： | Optimizing the Instruction Execution on the 603e |
| 中文描述： | 優(yōu)化了603e的指令執(zhí)行 |
| 文件頁數： | 40/54頁 |
| 文件大?。?/td> | 325K |
| 代理商： | INSTRUCTIN603EWP |
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RISC Microprocessor Division
Page 40
Although superscalar architectures feature multiple execution paths, resource limitations can stall full
utilization of these paths. Data cache misses are the primary cause of stalls in the LSU. The example
above demonstrates how stalls can occur because the 603e data cache can only handle one miss at a
time.
When a load or store misses in the data cache, the data cache asserts a busy signal that stalls
subsequent instructions in the LSU, as shown in
Figure 1
. While the data cache is busy, no other
instructions can access the data cache, and instructions are blocked from leaving the LSU EA stage.
This prevents a store from propagating from the LSU EA stage to the LSU store queue (LSU SQ), even
if the store queue is available.
For a load miss access, the data cache is busy until the data comes back from the BIU. For a store
miss access, the data cache is busy until the store is able to propagate to the BIU.
Figure 2
demonstrates store stalls. While load B is waiting for its data to come back, store A may not
access the data cache, and store C may not propagate to the LSU store queue. Note that load B
bypassed store A in the LSU.
Figure 3
demonstrates a load stall. Load D may not access the data cache until store A propagates to
the BIU. When it does, the data cache is no longer busy, and load D will bypass stores B and C.
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