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| 型號(hào)： | intel Pentium CPU |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit CPU With MMX Technology and Mobile Module(32位帶MMX和移動(dòng)模塊處理器) |
| 中文描述： | 32位CPU的MMX技術(shù)和移動(dòng)模塊（32位帶MMX公司和移動(dòng)模塊處理器） |
| 文件頁數(shù)： | 14/36頁 |
| 文件大小： | 395K |
| 代理商： | INTEL PENTIUM CPU |
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INTEL PENTIUM PROCESSOR WITH MMX TECHNOLOGY MOBILE MODULE
14
1/8/98 4:35 PM 24351502.DOC
2.1.7.
ITP/JTAG (7 SIGNALS)
Table 8 lists the
Intel Mobile Module’s In-target
Probe (ITP)/JTAG signals, which the system
electronics can use to implement a processor
debug port. The system manufacturer can use
debug port signals on development-level boards,
or on production boards for manufacturing
testability.
Please check with your local Intel Sales
Representative
for
recommendations and requirements for a debug
port.
further
details
on
Table 8. ITP/JTAG Pins
Name
Type
Voltage
Description
*TDO
O
V_CPUIO
JTAG Test Data Out:
Serial output port. TAP instructions and data are
shifted out of the processor from this port.
*TDI
I
V_CPUIO
JTAG Test Data In:
Serial input port. TAP instructions and data are
shifted into the processor from this port.
*TMS
I
V_CPUIO
JTAG Test Mode Select:
Controls the TAP controller change sequence.
*TCLK
I
V_CPUIO
JTAG Test Clock:
Testability clock for clocking the JTAG boundary scan
sequence.
*TRST#
I
V_CPUIO
JTAG Test Reset:
Asynchronously resets the TAP controller in the
processor.
*ITP(1:0)
ITP1: PRDY
ITP0: R/S#
O
I
V_CPUIO
Debug Port Signals:
Currently defined for the generation of Pentium
processors. Future uses are not yet defined.
* - Termination for the ITP signals must be done on the system electronics. The Intel Mobile Module does not
provide series termination for these signals.
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